JAJSGH0D november 2018 – october 2020 SN6505A-Q1 , SN6505B-Q1 , SN6505D-Q1
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| CLK | ||||||
| tCLKTIMER | Duration after which device switches to internal clock in case of invalid external clock | 10 | 25 | µs | ||
| OUTPUT STAGE | ||||||
| tBBM | Break-before-make time(SN6505A-Q1) | Measured as voltage with RL = 50 Ω to VCC, Refer to Figure 7-3 | 115 | ns | ||
| Break-before-make time (SN6505B-Q1 and SN6505D-Q1) | Measured as voltage with RL = 50 Ω to VCC, Refer to Figure 7-3 | 90 | ns | |||
| SOFT-START ENABLED (SN6505A-Q1 AND SN6505B-Q1) | ||||||
| tSS | Soft-start time (SN6505A-Q1) | 10% to 90% transition time on VOUT With transformer CLOAD = 40 µF RL = 5 Ω | 1 | 2.2 | 8 | ms |
| Soft-start time (SN6505B-Q1) | 10% to 90% transition time on VOUT With transformer CLOAD = 40 µF RL = 5 Ω | 1 | 4.25 | 8 | ms | |
| tSSdelay | Soft-start time delay | From power up to 90% transition time on VOUT With transformer CLOAD = 40 µF RL = 5 Ω | 3.5 | 8.5 | 18 | ms |
| SOFT-START DISABLED (SN6505D-Q1) | ||||||
| tPWRUP | Power up time | From EN=1 to full drive-current available at D1 and D2; 2.25 V ≤ VCC < 3 V | 75 | 160 | µs | |
| From EN=1 to full drive-current available at D1 and D2; 3 V ≤ VCC ≤ 5.5 V | 60 | 100 | µs | |||
| tPWRDN | Power down time | From EN=0 to output MOSFETs off (no current on D1 and D2) | 1 | 5 | µs | |