JAJSGI2G September   2015  – November 2018 SN6505A , SN6505B

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics, SN6505A
    8. 6.8 Typical Characteristics, SN6505B
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operating Mode
      3. 8.4.3 Shutdown-Mode
      4. 8.4.4 Spread Spectrum Clocking
      5. 8.4.5 External Clock Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Drive Capability
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
          3. 9.2.2.5.3 Recommended Transformers
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Application Circuits
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Recommended Transformers

Depending on the application, use the minimum configuration in Figure 46 or standard configuration in Figure 47.

SN6505A SN6505B Figure45_SLLSEP9_Q1.pngFigure 46. Unregulated Output for Low-Current Loads With Wide Supply Range
SN6505A SN6505B Figure46_sllsep9_Q1.pngFigure 47. Regulated Output for Stable Supplies and High Current Loads

The Wurth Electronics Midcom isolation transformers in Table 3 are optimized designs for the device, providing high efficiency and small form factor at low-cost.

The 1:1.1 and 1:1.7 turns-ratios are designed for logic applications with wide supply rails and low load currents. These applications operate without LDO, thus achieving further cost-reduction.

Table 3. Recommended Isolation Transformers Optimized for the Device

TURNS
RATIO
V × T
(Vμs)
ISOLATION
(VRMS)
DIMENSIONS
(mm)
APPLICATION LDO(1) ORDER NO. MANUFACTURER
1:1.1 ±2% 7 2500 6.73 x 10.05 x 4.19 3.3 V → 3.3 V, 100mA, SN6505B
Refer to Figure 13 and Figure 14
No 760390011 Wurth Electronics / Midcom
1:1.1 ±2% 11 5 V → 5 V, 100mA, SN6505B
Refer to Figure 15 and Figure 16
760390012
1:1.7 ±2% 3.3 V → 5 V, 100mA, SN6505B
Refer to Figure 17 and Figure 18
760390013
1:1.3 ±2% 3.3 V → 3.3 V, 100mA, SN6505B
Refer to Figure 19 and Figure 20
Yes 760390014
1:1.3 ±2% 5 V → 5 V, 100mA, SN6505B
Refer to Figure 21 and Figure 22
760390014
1:2.1 ±2% 3.3 V → 5 V, 100mA, SN6505B
Refer to Figure 23 and Figure 24
760390015
1.23:1 ±2% 5 V → 3.3 V, 100mA, SN6505B 750313710
1:1.7 ±2% 8.9 8.3 x 12.6 x 4.1 3.3 V → 3.3 V, 1A, SN6505B
Refer to Figure 25 and Figure 26
750316028
1:2.1 ±2% 3.3 V → 5 V, 1A, SN6505B
Refer to Figure 27 and Figure 28
No 750316029
1.3:1 ±2% 10.8 5 V → 3.3 V, 1A, SN6505B
Refer to Figure 29 and Figure 30
750316030
1:1.1 ±2% 8.6 3.3 V → 3.3 V , 1A , SN6505B
5 V → 5 V , 1A , SN6505B
Refer to Figure 11 and Figure 12
750315371
1:1.1 ±2% 11 5000 9.14 x 12.7 x 7.37 3.3 V → 3.3 V, 100mA, SN6505B 750313734
1:1.1 ±2% 5 V → 5 V, 100mA, SN6505B 750313734
1:1.7 ±2% 3.3 V → 5 V, 100mA, SN6505B 750313769
1:1.3 ±2% 3.3 V → 3.3 V, 100mA, SN6505B
5 V → 5 V, 100mA, SN6505B
Yes 750313638
1:2.1 ±2% 3.3 V → 5 V, 100mA, SN6505B 750313626
1.3:1 ±2% 5 V → 3.3 V, 100mA , SN6505B No 750313638
1:1.75 ±2% 41 12.32 x 15.41 x 11.05 3.3 V → 3.3 V, 1A, SN6505A
Refer to Figure 3 and Figure 4
Yes 750316031
1:2 ±2% 3.3 V → 5 V, 1A, SN6505A
Refer to Figure 5 and Figure 6
No 750316032
1.3:1 ±2% 42 5.0 V → 3.3 V, 1A, SN6505A
Refer to Figure 7 and Figure 8
750316033
1:1.1 ±2% 23 14.88 x 12.32 x 11.05 3.3 V → 3.3 V, 1A, SN6505A
5 V → 5 V, 1A , SN6505A
Refer to Figure 1 and Figure 2
750315240
For configurations with LDO, a higher voltage than the required output voltage is generated, to allow for LDO drop-out. Figures show the voltage and efficiency at the LDO input.