JAJSCG0A September   2016  – November 2016 SN65HVD233-Q1 , SN65HVD234-Q1 , SN65HVD235-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: Driver
    6. 8.6  Electrical Characteristics: Receiver
    7. 8.7  Switching Characteristics: Driver
    8. 8.8  Switching Characteristics: Receiver
    9. 8.9  Switching Characteristics: Device
    10. 8.10 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1 Diagnostic Loopback (SN65HVD233-Q1)
      2. 10.3.2 Autobaud Loopback (SN65HVD235-Q1)
      3. 10.3.3 Slope Control
      4. 10.3.4 Standby
      5. 10.3.5 Thermal Shutdown
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Bus Loading, Length and Number of Nodes
        2. 11.2.1.2 CAN Termination
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curve
    3. 11.3 System Example
      1. 11.3.1 ISO 11898 Compliance of SN65HVD23x-Q1 Family of 3.3-V CAN Transceivers
        1. 11.3.1.1 Introduction
        2. 11.3.1.2 Differential Signal
        3. 11.3.1.3 Common-Mode Signal
        4. 11.3.1.4 Interoperability of 3.3-V CAN in 5-V CAN Systems
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 関連リンク
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

D Package
8-Pin SOIC
SN65HVD233-Q1 Top View
D Package
8-Pin SOIC
SN65HVD234-Q1 Top View
D Package
8-Pin SOIC
SN65HVD235-Q1 Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
'233-Q1 '234-Q1 '235-Q1
AB — — 5 I SN65HVD235-Q1 device: Autobaud loopback mode-input pin (AB). Can be tied to ground if not used. Can also be left open if unused because the internal pulldown biases this toward ground.
CANH 7 7 7 I/O High-level CAN bus line
CANL 6 6 6 I/O Low-level CAN bus line
EN — 5 — I SN65HVD234-Q1 device: Enable input pin. Logic high for enabling a normal mode (high-speed or slope-control mode). Logic low for sleep mode. (EN)
GND 2 2 2 — Ground connection
LBK 5 — — I SN65HVD233-Q1 device: Loopback-mode input pin (LBK). Can be tied to ground if not used. Can also be left open if unused because the internal pulldown biases this toward ground.
RS 8 8 8 I Mode-select pin: strong pulldown to GND = high-speed mode, strong pullup to VCC = low-power mode, 10-kΩ to 100-kΩ pulldown to GND = slope-control mode
RXD 4 4 4 O CAN receive data output (LOW for dominant and HIGH for recessive bus states)
TXD 1 1 1 I CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
VCC 3 3 3 I Transceiver 3.3-V supply voltage