JAJSF06A March   2018  – May 2018 SN65LVDS93B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ディスクリートLVDS TXを使用するRGBビデオ・システム
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TTL Input Data
      2. 9.3.2 LVDS Output Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Edge
      2. 9.4.2 Low Power Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power
        2. 10.2.2.2 Signal Connectivity
        3. 10.2.2.3 PCB Routing
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Stackup
      2. 12.1.2 Power and Ground Planes
      3. 12.1.3 Traces, Vias, and Other PCB Components
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS MIN TYP(1) MAX UNIT
t0 Delay time, CLKOUT↑ after Yn valid (serial bit position 0, equal D1, D9, D20, D5) See Figure 8, tC = 10 ns,
|Input clock jitter| < 25 ps (2) 		–0.1 0 0.1 ns
t1 Delay time, CLKOUT↑ after Yn valid (serial bit position 1, equal D0, D8, D19, D27) 1/7 tc – 0.1 1/7 tc + 0.1 ns
t2 Delay time, CLKOUT↑ after Yn valid (serial bit position 2, equal D7, D18, D26. D23) 2/7 tc – 0.1 2/7 tc + 0.1 ns
t3 Delay time, CLKOUT↑ after Yn valid (serial bit position 3; equal D6, D15, D25, D17) 3/7 tc – 0.1 3/7 tc + 0.1 ns
t4 Delay time, CLKOUT↑ after Yn valid (serial bit position 4, equal D4, D14, D24, D16) 4/7 tc – 0.1 4/7 tc + 0.1 ns
t5 Delay time, CLKOUT↑ after Yn valid (serial bit position 5, equal D3, D13, D22, D11) 5/7 tc – 0.1 5/7 tc + 0.1 ns
t6 Delay time, CLKOUT↑ after Yn valid (serial bit position 6, equal D2, D12, D21, D10) 6/7 tc – 0.1 6/7 tc + 0.1 ns
tc(o) Output clock period tc ns
Δtc(o) Output clock cycle-to-cycle jitter (3) tC = 10 ns; clean reference clock, see Figure 9 ±35 ps
tC = 10 ns with 0.05UI added noise modulated at 3 MHz, see Figure 9 ±44
tC = 7.4 ns; clean reference clock, see Figure 9 ±35
tC = 7.4 ns with 0.05UI added noise modulated at 3 MHz, see Figure 9 ±42
tw High-level output clock pulse duration 4/7 tc ns
tr/f Differential output voltage transition time (tr or tf) See Figure 5 225 500 ps
ten Enable time, SHTDN↑ to phase lock (Yn valid) f(clk) = 85 MHz, See Figure 10 10 µs
tdis Disable time, SHTDN↓ to off-state (CLKOUT high-impedance) f(clk) = 85 MHz, See Figure 11 12 ns
(1) All typical values are at VCC = 3.3V,TA = 25°C.
(2) |Input clock jitter| is the magnitude of the change in theinputclock period.
(3) The output clock cycle-to-cycle jitter is the largestrecordedchange in the output clock period from one cycle to the next cycle observed over15,000cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimumjittervalue.
SN65LVDS93B load_seq_lls846.gifFigure 1. Typical SN65LVDS93B Load and Shift Sequences