JAJSGX8C April   2002  – February 2019 SN65LVDT14 , SN65LVDT41

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      SN65LVDT41 の機能図
      2.      SN65LVDT14 の機能図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     SN65LVDT41 Pin Functions
    2.     SN65LVDT14 Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Receiver Electrical Characteristics
    6. 7.6  Driver Electrical Characteristics
    7. 7.7  Device Electrical Characteristics
    8. 7.8  Receiver Switching Characteristics
    9. 7.9  Driver Switching Characteristics
    10. 7.10 Typical Characteristics
      1. 7.10.1 Receiver
      2. 7.10.2 Driver
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 SN65LVDTxx Driver and Receiver Functionality
      2. 9.3.2 Integrated Termination
      3. 9.3.3 SN65LVDTxx Equivalent Circuits
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Extending a Serial Peripheral Interface Using LVDS Signaling Over Differential Transmission Cables
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 SPI Propagation Delay Limitations
        2. 10.2.2.2 Interconnecting Media
        3. 10.2.2.3 Input Fail-Safe Biasing
        4. 10.2.2.4 Power Decoupling Recommendations
        5. 10.2.2.5 PCB Transmission Lines
        6. 10.2.2.6 Probing LVDS Transmission Lines on PCB
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip vs. Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
      6. 12.1.6 Decoupling
    2. 12.2 Layout Examples
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 関連リンク
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|20
サーマルパッド・メカニカル・データ
発注情報

8 Parameter Measurement Information

SN65LVDT14 SN65LVDT41 vdef_lls530.gifFigure 8. Receiver Voltage Definitions

Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages

APPLIED VOLTAGES RESULTING DIFFERENTIAL
INPUT VOLTAGE		 RESULTING
COMMON-MODE
INPUT VOLTAGE
VIA VIB VID VIC
1.25 V 1.15 V 100 mV 1.2 V
1.15 V 1.25 V –100 mV 1.2 V
2.4 V 2.3 V 100 mV 2.35 V
2.3 V 2.4 V –100 mV 2.35 V
0.1 V 0.0 V 100 mV 0.05 V
0.0 V 0.1 V –100 mV 0.05 V
1.5 V 0.9 V 600 mV 1.2 V
0.9 V 1.5 V –600 mV 1.2 V
2.4 V 1.8 V 600 mV 2.1 V
1.8 V 2.4 V –600 mV 2.1 V
0.6 V 0.0 V 600 mV 0.3 V
0.0 V 0.6 V –600 mV 0.3 V
SN65LVDT14 SN65LVDT41 cdef_lls530.gifFigure 9. Driver Voltage and Current Definitions
SN65LVDT14 SN65LVDT41 pmi_ttest_lls530.gifFigure 10. Receiver Timing Test Circuit
SN65LVDT14 SN65LVDT41 pmi_wave_lls530.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 11. Receiver Timing Test Circuit Waveforms
SN65LVDT14 SN65LVDT41 pmi_dtcir_lls530.gifFigure 12. Driver VDO Test Circuit
SN65LVDT14 SN65LVDT41 pmi_ovolt_lls530.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 1 GHz.
Figure 13. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
SN65LVDT14 SN65LVDT41 pmi_osig_lls530.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T.
Figure 14. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal