JAJSGX8C April   2002  – February 2019 SN65LVDT14 , SN65LVDT41

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      SN65LVDT41 の機能図
      2.      SN65LVDT14 の機能図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     SN65LVDT41 Pin Functions
    2.     SN65LVDT14 Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Receiver Electrical Characteristics
    6. 7.6  Driver Electrical Characteristics
    7. 7.7  Device Electrical Characteristics
    8. 7.8  Receiver Switching Characteristics
    9. 7.9  Driver Switching Characteristics
    10. 7.10 Typical Characteristics
      1. 7.10.1 Receiver
      2. 7.10.2 Driver
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 SN65LVDTxx Driver and Receiver Functionality
      2. 9.3.2 Integrated Termination
      3. 9.3.3 SN65LVDTxx Equivalent Circuits
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Extending a Serial Peripheral Interface Using LVDS Signaling Over Differential Transmission Cables
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 SPI Propagation Delay Limitations
        2. 10.2.2.2 Interconnecting Media
        3. 10.2.2.3 Input Fail-Safe Biasing
        4. 10.2.2.4 Power Decoupling Recommendations
        5. 10.2.2.5 PCB Transmission Lines
        6. 10.2.2.6 Probing LVDS Transmission Lines on PCB
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip vs. Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
      6. 12.1.6 Decoupling
    2. 12.2 Layout Examples
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 関連リンク
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • PW|20
サーマルパッド・メカニカル・データ
発注情報

Extending a Serial Peripheral Interface Using LVDS Signaling Over Differential Transmission Cables

Serial Peripheral Interface (SPI) is found in numerous applications as the communication method between processor and peripheral devices using single-ended signals over short distances. However, there is increasing demand for longer range SPI communication on the same PCB or from board to board. As distance increases, external noise, and electromagnetic interference (EMI) with single-ended SPI signals becomes an issue. Furthermore, increased distance limits the data rate due to propagation delay, and affects the signal quality due to potential ground shift between boards. A long distance SPI communication is achievable with the help of LVDS. LVDS, as specified by the TIA/EIA-644-A standard, provides several benefits when compared to alternative long-distance signaling technologies: low EMI, high noise immunity, low power consumption, and inexpensive interconnect cables.

SPI operates in a master-slave architecture, with four unidirectional signal lines. The master supplies data named Master-Out-Slave-In (MOSI), a clock (SCK), and a optional Chip Select (CS) signal to control the operation of the system with multiple slave devices. The MOSI,SCLK, and CS signals are unidirectional from the master device to slave devices. The serial data from slave to master device is a unidirectional signal named Master-In-Slave-Out (MISO). The flow of data can be seen in Figure 18.

SN65LVDT14 and SN65LVDT41 provide the necessary LVDS drivers and receivers specifically targeted at implementing a long distance SPI application. It uses the unidrectional links for the MOSI, MISO, SCK, and CS signals and converts the single-ended data into a unidirectional LVDS links.SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package should be located at the SPI master device. SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package and should be located at the SPI device.

SN65LVDT14 SN65LVDT41 Typ_spi_solution.pngFigure 18. Typical SPI Application With LVDS

Table 4. SPI Design Parameters

Design Parameter Example Value
Supply Voltage (VDD) 3 to 3.6 V
Single-ended Input Voltage 0 to VDD
SPI Data Rate 0 to 10 Mbps
Interconnect Characteristic Impedance 100 Ω
Number of LVDS Channel 4
Number of Transmitter Nodes 3
Number of Receiver Nodes 1
Ground shift between driver and receiver ±1 V