SCLS376I June   1997  – March 2015 SN54AHC273 , SN74AHC273

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematics
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, VCC = 3.3 V ± 0.3 V
    7. 7.7  Timing Requirements, VCC = 5 V ± 0.5 V
    8. 7.8  Switching Characteristics, VCC = 3.3 V ± 0.3 V
    9. 7.9  Switching Characteristics, VCC = 5 V ± 0.5 V
    10. 7.10 Noise Characteristics
    11. 7.11 Operating Characteristics
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DGV|20
  • DB|20
  • NS|20
  • N|20
  • DW|20
  • PW|20
サーマルパッド・メカニカル・データ
発注情報

9 Detailed Description

9.1 Overview

These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

The inputs are 5 V tolerant and can be driven from 5-V devices. This feature allows the use of these devices as down translators in a mixed 5-V to 3.3-V system environment.

9.2 Functional Block Diagrams

SN54AHC273 SN74AHC273 ld1_cls376.gif
 
SN54AHC273 SN74AHC273 ld2_cls376.gif

9.3 Feature Description

  • Wide operating voltage range
    • Operates from 2 V to 5.5 V
  • Allows down voltage translation
    • Inputs accept voltages to 5.5 V
  • Slow edge rates minimize output ringing

9.4 Device Functional Modes

Table 1. Function Table

INPUTS OUTPUT
Y
CLR CLK D
L X X L
H ↑ H H
H ↑ L L
H L X Q0