SCES604J SEPTEMBER 2004 – December 2016 SN74AUP1G00
This is a single 2-input positive-NAND gate that is designed in Texas Instrument’s ultra-low power technology. It performs the Boolean function Y = A × B or Y = A + B in positive logic.
The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered. The Ioff feature also allows for live insertion.
Table 1 shows the functional modes of the SN74AUP1G00 device.