SCES593F JULY   2004  – July 2017 SN74AUP1G80


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: TA = 25°C
    6. 6.6  Electrical Characteristics: TA = -40°C to +85°C
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics: CL = 5 pF
    9. 6.9  Switching Characteristics: CL = 10 pF
    10. 6.10 Switching Characteristics: CL = 15 pF
    11. 6.11 Switching Characteristics: CL = 30 pF
    12. 6.12 Operating Characteristics
    13. 6.13 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Duration
    2. 7.2 Enable and Disable Times
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-Voltage Tolerant Inputs
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information



Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

A useful application for the SN74AUP1G80 is using it as a frequency divider. By feeding back the output (Q) to the input (D), the output toggles on every rising edge of the clock waveform. The output goes HIGH once every two clock cycles, so essentially the frequency of the clock signal is divided by a factor of two. The device does not have preset or clear functions so the initial state of the output is unknown. This application implements the use of an override pin to initially set the input HIGH or LOW. Initialization is not needed, but should be kept in mind. Post initialization, the Override input is set to a high-impedance mode, or it can be used to force a HIGH or LOW output.

Typical Application

SN74AUP1G80 SN74AUP1G80_Application1.gif Figure 7. Clock Frequency Division

Design Requirements

For this application, a resistor must be placed on the feedback line in order for the initialization voltage from the override input to overpower the signal coming from the output (Q). Without a resistor the state at the input would be unknown as the output of the SN74AUP1G80 is driving the line separate from the Override input.

The SN74AUP1G80 device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits.

Detailed Design Procedure

  1. Recommended input conditions:
  2. Recommended output conditions:
  3. Feedback resistor:
    • A 10-kΩ resistor is chosen to bias the input so the Override input can initialize the input and output. The resistor value is important because a resistance too high, such as 1 MΩ, would cause too much of a voltage drop, causing the output to no longer be able to drive the input. On the other hand, a resistor too low, such as a 1 Ω, would not bias enough and might cause bus contention between the Q output and the override input, possibly damaging the device.

Application Curve

SN74AUP1G80 schem-01-sces221.gif Figure 8. Frequency Division