JAJSGK7C December   2018  – September 2020 SN74AXCH1T45

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Operating Characteristics: TA = 25°C
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Standard CMOS Inputs
      2. 8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 VCC Isolation
      5. 8.3.5 Over-voltage Tolerant Inputs
      6. 8.3.6 Negative Clamping Diodes
      7. 8.3.7 Fully Configurable Dual-Rail Design
      8. 8.3.8 Supports High-Speed Translation
      9. 8.3.9 Bus-Hold Data Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Enable Times
    2. 9.2 Typical Applications
      1. 9.2.1 Interrupt Request Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Universal Asynchronous Receiver-Transmitter (UART) Interface Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1 Interrupt Request Application

Figure 9-1 shows an example of the SN74AXCH1T45 being used in an application where a system controller flags an interrupt request (IRQ) to the CPU. The system controller determines the direction of the IRQ line to either flag an interrupt to the CPU or allow the CPU to drive data on the line. In this application the controller is operating at 3.3 V while the CPU can be operating as low as 0.65 V.

The SN74AXCH1T45 device is used to ensure that these devices can communicate at the appropriate voltage levels. Because the SN74AXCH1T45 does not have an output-enable ( OE) pin, the system designer should take precautions to avoid bus contention between the CPU and controller when changing directions.

GUID-9FEC867A-AB81-43BA-B13B-580D7259859E-low.gifFigure 9-1 Interrupt Request Application