JAJSH48 March   2019 SN74AXCH4T245

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics, VCCA = 0.7 ± 0.05 V
    7. 7.7  Switching Characteristics, VCCA = 0.8 ± 0.04 V
    8. 7.8  Switching Characteristics, VCCA = 0.9 ± 0.045 V
    9. 7.9  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    10. 7.10 Switching Characteristics, VCCA = 1.5 ± 0.1 V
    11. 7.11 Switching Characteristics, VCCA = 1.8 ± 0.15 V
    12. 7.12 Switching Characteristics, VCCA = 2.5 ± 0.2 V
    13. 7.13 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    14. 7.14 Operating Characteristics: TA = 25°C
    15. 7.15 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Load Circuit and Voltage Waveforms
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Standard CMOS Inputs
      2. 9.3.2  Balanced High-Drive CMOS Push-Pull Outputs
      3. 9.3.3  Partial Power Down (Ioff)
      4. 9.3.4  VCC Isolation
      5. 9.3.5  Over-voltage Tolerant Inputs
      6. 9.3.6  Glitch-free Power Supply Sequencing
      7. 9.3.7  Negative Clamping Diodes
      8. 9.3.8  Fully Configurable Dual-Rail Design
      9. 9.3.9  Supports High-Speed Translation
      10. 9.3.10 Bus-Hold Data Inputs
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.6 Glitch-free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the output erroneously transitions to VCC when it should be held low). Glitches of this nature can be misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device configuration of the peripheral, or even a false data initialization by the peripheral. For more information regarding the power up glitch performance of the AXC family of level translators, see the Glitch Free Power Sequencing With AXC Level Translators application report