JAJSJI0D September   1988  – February 2021 SN74BCT374

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     4
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions (1)
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bipolar Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Power Considerations
        2. 9.2.2.2 Output Considerations
        3. 9.2.2.3 Input Considerations
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • NS|20
  • N|20
  • DW|20
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

All parameters and waveforms are not applicable to all devices.

GUID-20200909-CA0I-NQNR-1QHP-XHMBDGDHJGTF-low.gif
A. CL includes probe and jig capacitance.
B. When measuring propagation delay times of 3-state outputs, switch S1 is open.
Figure 7-1 Load circuit for
3-state and open-collector outputs
GUID-20200909-CA0I-LTJL-G1XN-PC4LDXWJP83L-low.gif
A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
Figure 7-3 Voltage waveforms
Setup and hold times
GUID-20200909-CA0I-PNLP-L3SK-B2HH2MGLHHTS-low.gif
A. The outputs are measured one at a time with one transition per measurement.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
Figure 7-5 Voltage waveforms
Propagation delay times
GUID-20200909-CA0I-RJK1-QPMS-1GTXBKN048HC-low.gif
A. CL includes probe and jig capacitance.
Figure 7-2 Load circuit for
push-pull outputs
GUID-20200909-CA0I-PRZ2-BBMW-0KZJB8JL4Q2J-low.gif
A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
Figure 7-4 Voltage waveforms
Pulse duration
GUID-20200909-CA0I-0VSS-V2V7-FCPP4T45DT7D-low.gif
A. The outputs are measured one at a time with one transition per measurement.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
Figure 7-6 Voltage waveforms
Enable and disable times, 3-state outputs