JAJSNM0A
July 2022 – December 2022
SN74LV165A-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements, VCC = 2.5 V ± 0.2 V
6.7
Timing Requirements, VCC = 3.3 V ± 0.3 V
6.8
Timing Requirements, VCC = 5 V ± 0.5 V
6.9
Switching Characteristics, VCC = 2.5 V ± 0.2 V
6.10
Switching Characteristics, VCC = 3.3 V ± 0.3 V
6.11
Switching Characteristics, VCC = 5 V ± 0.5 V
6.12
Operating Characteristics
6.13
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS Push-Pull Outputs
8.3.2
Latching Logic
8.3.3
Partial Power Down (Ioff)
8.3.4
Wettable Flanks
8.3.5
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Power Considerations
9.2.2
Input Considerations
9.2.3
Output Considerations
9.2.4
Detailed Design Procedure
9.2.5
Application Curves
10
Power Supply Recommendations
11
レイアウト
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
サポート・リソース
12.4
Trademarks
12.5
静電気放電に関する注意事項
12.6
用語集
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
BQB|16
MPQF539A
サーマルパッド・メカニカル・データ
BQB|16
PPTD365
発注情報
jajsnm0a_oa
jajsnm0a_pm
8.3
Feature Description