SCAS293M January   1993  – June 2026 SN74LVC240A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   5
  6.   6
  7. 4 Pin Configuration and Functions
  8. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics, –40°C to 85°C
    7. 5.7 Switching Characteristics, –40°C to 125°C
    8. 5.8 Operating Characteristics
    9. 5.9 Typical Characteristics
  9. 6 Parameter Measurement Information
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Partial Power Down (Ioff)
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  11. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  12. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  13.   49
  14. 10Revision History
  15. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DGV|20
  • DB|20
  • NS|20
  • DW|20
  • PW|20
  • DGS|20
サーマルパッド・メカニカル・データ
発注情報

10 Revision History

Changes from July 1, 2014 to June 25, 2026 (from Revision L (July 2014) to Revision M (June 2026))

  • Updated the numbering format for tables, figures, and cross-references throughout the document Go
  • Moved ESD ratings to ESD Ratings tableGo
  • Updated latch-up ratings to latest standardsGo
  • Updated Device Information format and included package sizeGo
  • Updated Simplified Schematic Go
  • Updated Applications Go
  • Added DGS and RKS package informationGo
  • Added DGS and RKS package informationGo
  • Added ESD Ratings tableGo
  • Changed Junction-to-ambient thermal resistance value for PW package from: 102.5°C/W to: 120.3°C/W Go
  • Changed Junction-to-case (top) thermal resistance value for PW package from: 35.9°C/W to: 62.5°C/WGo
  • Changed Junction-to-board thermal resistance value for PW package from: 53.5°C/W to: 82.4°C/WGo
  • Changed Junction-to-top characterization value for PW package from: 2.2°C/W to: 16.0°C/WGo
  • Changed Junction-to-board characterization value for PW package from: 52.9°C/W to: 81.5°C/WGo
  • Added DW, DB and NS package Thermal Information table.Go
  • Added parallel trace spacing recommendation to layout guidelines. Changed wording of "Avoid branches; buffer signals that must branch separately" to "Avoid branches; buffer each signal that must branch separately"Go
  • Updated Detailed Description, Application and Implementation and Device Documentation sectionsGo

Changes from Revision K (February 2005) to Revision L (July 2014)

  • Updated document to new TI data sheet standards.Go
  • Deleted Ordering Information table.Go
  • Updated Ioff bullet in Features list.Go
  • Added Device Information table.Go
  • Changed MAX ambient temperature to 125°C in Recommended Operating Conditions table.Go
  • Added Thermal Information table.Go
  • Added –40°C to 125°C temperature range to Electrical Characteristics table.Go
  • Added Switching Characteristics table for –40°C to 125°C temperature range.Go
  • Added Typical Characteristics. Go
  • Added Detailed Description sectionGo
  • Added Application and Implementation sectionGo