SCES193N April   1999  – January 2015 SN74LVC2G00

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Switching Characteristics, -40°C to 125°C
    5. 7.5 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DCU|8
  • YZP|8
  • DCT|8
サーマルパッド・メカニカル・データ
発注情報

9 Detailed Description

9.1 Overview

The SN74LVC2G00 device contains two 2-input positive-NAND gates and performs the Boolean function
Y = A × B or Y = A + B on each gate. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

9.2 Functional Block Diagram

LD_CES193.gif

9.3 Feature Description

  • Wide operating voltage range.
    • Operates from 1.65 V to 5.5 V
  • Allows down voltage translation
    • Inputs accept voltages to 5.5 V
  • Ioff feature
    • Allows voltages on the inputs and outputs, when VCC is 0 V

9.4 Device Functional Modes

Table 1. Function Table (Each Gate)

INPUTS OUTPUT
Y
A B
H H L
L X H
X L H