JAJSPG8I August   1987  – January 2023 SN65ALS176 , SN75ALS176 , SN75ALS176A , SN75ALS176B

PRODUCTION DATA  

  1. 1 特長
  2. 2 概要
  3. 3 改訂履歴
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  推奨動作条件
    3. 5.3  Thermal Information
    4. 5.4  Electrical Characteristics - Driver
    5. 5.5  Switching Characteristics - Driver
    6. 5.6  Switching Characteristics - Driver
    7. 5.7  Symbol Equivalents
    8. 5.8  Electrical Characteristics - Receiver
    9. 5.9  Switching Characteristics - Receiver
    10. 5.10 Switching Characteristics - Receiver
    11. 5.11 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • P|8
サーマルパッド・メカニカル・データ
発注情報

5.5 Switching Characteristics - Driver

SN65ALS176

over recommended ranges of supply voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP#GUID-B79B9DAB-AB21-424A-BB43-8C46E85D9BC0 MAX UNIT
td(OD) Differential output delay time RL = 54 Ω CL = 50 pF, See GUID-1D3EE06C-51AC-4996-BDD0-45715DC48B44.html#FIG_BL2_V3M_25B 15 ns
tsk(p) Pulse skew#GUID-C331AFFE-3D12-4513-88EE-BDCF416C528D RL = 54 Ω CL = 50 pF, See GUID-1D3EE06C-51AC-4996-BDD0-45715DC48B44.html#FIG_BL2_V3M_25B 0 2 ns
tsk(lim) Pulse skew#GUID-480FA524-4E75-425D-8F1A-7C1E6095AEEC RL = 54 Ω CL = 50 pF, See GUID-1D3EE06C-51AC-4996-BDD0-45715DC48B44.html#FIG_BL2_V3M_25B 15 ns
tt(OD) Differential output transition time RL = 54 Ω CL = 50 pF, See GUID-1D3EE06C-51AC-4996-BDD0-45715DC48B44.html#FIG_BL2_V3M_25B 8 ns
tPZH Output enable time to high level RL = 110 Ω CL = 50 pF, See GUID-1D3EE06C-51AC-4996-BDD0-45715DC48B44.html#FIG_Z13_V3M_25B 80 ns
tPZL Output enable time to low level RL = 110 Ω CL = 50 pF, See GUID-1D3EE06C-51AC-4996-BDD0-45715DC48B44.html#FIG_PPL_V3M_25B 30 ns
tPHZ Output disable time from high level RL = 110 Ω CL = 50 pF, See GUID-1D3EE06C-51AC-4996-BDD0-45715DC48B44.html#FIG_Z13_V3M_25B 50 ns
tPLZ Output disable time from low level RL = 110 Ω CL = 50 pF, See GUID-1D3EE06C-51AC-4996-BDD0-45715DC48B44.html#FIG_PPL_V3M_25B 30 ns
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) Pulse skew is defined as the |tPLH– tPHL| of each channel of the same device.
(3) Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.