JAJSUH1 April   2024 TAS2505A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  I2S/LJF/RJF Timing in Master Mode
    7. 5.7  I2S/LJF/RJF Timing in Slave Mode
    8. 5.8  DSP Timing in Master Mode
    9. 5.9  DSP Timing in Slave Mode
    10. 5.10 I2C Interface Timing
    11. 5.11 SPI Interface Timing
    12. 5.12 Typical Characteristics
      1. 5.12.1 Class D Speaker Driver Performance
      2. 5.12.2 HP Driver Performance
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Analog I/O
      2. 7.3.2 Audio DAC and Audio Analog Outputs
      3. 7.3.3 DAC
      4. 7.3.4 POR
      5. 7.3.5 CLOCK Generation and PLL
      6. 7.3.6 Speaker Driver
      7. 7.3.7 Automotive Diagnostics
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Pins
      2. 7.4.2 Analog Pins
      3. 7.4.3 Multifunction Pins
      4. 7.4.4 Analog Signals
        1. 7.4.4.1 Analog Inputs AINL and AINR
      5. 7.4.5 DAC Processing Blocks — Overview
      6. 7.4.6 Digital Mixing and Routing
      7. 7.4.7 Analog Audio Routing
      8. 7.4.8 5V LDO
      9. 7.4.9 Digital Audio and Control Interface
        1. 7.4.9.1 Digital Audio Interface
        2. 7.4.9.2 Control Interface
          1. 7.4.9.2.1 I2C Control Mode
          2. 7.4.9.2.2 SPI Digital Interface
        3. 7.4.9.3 Device Special Functions
    5. 7.5 Register Map
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Circuit Configuration With Internal LDO
        1. 9.2.2.1 Design Requirements
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Pad
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
    8. 10.8 Community Resources
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1.2 Detailed Design Procedure

In this application, the device is able to use both digital and analog inputs, working in mono output by summing left and right analog inputs and output from DAC and routing this signal into the speaker output.

The internal LDO is not used in this application becasuse the LDO_SEL pin is tied to GND. External 1.8V supply is used to power AVDD and DVDD. IOVDD can be supplied by voltages between 1.1V and 3.6V which lets the system to use conventional 1.8V or 3.3V supplies. The SPKVDD can be connected to voltages between 2.7V and 5.5V, although it is usually supplied by a 5V voltage.

Decoupling capacitors should be used at all the supply lines. TI recommends using 0.1µF, 10µF, and 22µF capacitors for a better system performance.

Decoupling series capacitors must be used at the analog input.

All grounds are tied together; route analog and digital paths are separated to avoid interference.