SLAS898B January   2014  – April 2015 TAS2552

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements/Timing Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  General I2C Operation
      2. 7.3.2  Single-Byte and Multiple-Byte Transfers
      3. 7.3.3  Single-Byte Write
      4. 7.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 7.3.5  Single-Byte Read
      6. 7.3.6  Multiple-Byte Read
      7. 7.3.7  PLL
      8. 7.3.8  Gain Settings
      9. 7.3.9  Class-D Edge Rate Control
      10. 7.3.10 Battery Tracking AGC
      11. 7.3.11 Configurable Boost Current Limit (ILIM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Audio Digital I/O Interface
        1. 7.4.1.1 Right-Justified Mode
        2. 7.4.1.2 Left-Justified Mode
        3. 7.4.1.3 I2S Mode
        4. 7.4.1.4 Audio Data Serial Interface Timing (I2S, Left-Justified, Right-Justified Modes)
        5. 7.4.1.5 DSP Mode
        6. 7.4.1.6 DSP Timing
      2. 7.4.2 TDM Mode
      3. 7.4.3 PDM Mode
        1. 7.4.3.1 DOUT Timing - PDM Output Mode
    5. 7.5 Register Map
      1. 7.5.1  Register Map Summary
      2. 7.5.2  Register 0x00: Device Status Register
      3. 7.5.3  Register 0x01: Configuration Register 1
      4. 7.5.4  Register 0x02: Configuration Register 2
      5. 7.5.5  Register 0x03: Configuration Register 3
      6. 7.5.6  Register 0x04: DOUT Tristate Mode
      7. 7.5.7  Register 0x05: Serial Interface Control Register 1
      8. 7.5.8  Register 0x06: Serial Interface Control Register 2
      9. 7.5.9  Register 0x07: Output Data Register
      10. 7.5.10 Register 0x08: PLL Control Register 1
      11. 7.5.11 Register 0x09: PLL Control Register 2
      12. 7.5.12 Register 0x0A: PLL Control Register 3
      13. 7.5.13 Register 0x0B: Battery Tracking Inflection Point Register
      14. 7.5.14 Register 0x0C: Battery Tracking Slope Control Register
      15. 7.5.15 Register 0x0D: Reserved Register
      16. 7.5.16 Register 0x0E: Battery Tracking Limiter Attack Rate and Hysteresis Time
      17. 7.5.17 Register 0x0F: Battery Tracking Limiter Release Rate
      18. 7.5.18 Register 0x10: Battery Tracking Limiter Integration Count Control
      19. 7.5.19 Register 0x11: PDM Configuration Register
      20. 7.5.20 Register 0x12: PGA Gain Register
      21. 7.5.21 Register 0x13: Class-D Edge Rate Control Register
      22. 7.5.22 Register 0x14: Boost Auto-Pass Through Control Register
      23. 7.5.23 Register 0x15: Reserved Register
      24. 7.5.24 Register 0x16: Version Number
      25. 7.5.25 Register 0x17: Reserved Register
      26. 7.5.26 Register 0x18: Reserved Register
      27. 7.5.27 Register 0x19: VBAT Data Register
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application - Digital Audio Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Audio Input/Output
          2. 8.2.1.2.2 Mono/Stereo Configuration
          3. 8.2.1.2.3 Boost Converter Passive Devices
          4. 8.2.1.2.4 EMI Passive Devices
          5. 8.2.1.2.5 Miscellaneous Passive Devices
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Typical Application - Analog Audio Input
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Audio Input/Output
        3. 8.2.2.3 Application Performance Plots
      3. 8.2.3 Typical Application - Maximum Output Power, Analog Audio Input
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Performance Plots
    3. 8.3 Initialization
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
    2. 9.2 Power Supply Sequencing
    3. 9.3 Boost Supply Details
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Package Dimensions
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Applications and Implementation

8.1 Application Information

The TAS2552 is a digital or analog input high efficiency Class-D audio power amplifier with advanced battery current management and an integrated Class-G boost converter. In auto passthrough mode, the Class-G boost converter generates the Class-D amplifier supply rail. During low Class-D output power, the boost improves efficiency by deactivating and connecting VBAT directly to the Class-D amplifier supply. When high power audio is required, the boost quickly activates to provide louder audio than a stand-alone amplifier connected directly to the battery. To enable load monitoring, the TAS2552 constantly measures the current and voltage across the load and provides a digital stream of this information back to a processor.

8.2 Typical Applications

8.2.1 Typical Application - Digital Audio Input

TAS2552 Apps_Diagram_Digital_Input.gifFigure 50. Typical Application Schematic

Table 12. Recommended External Components

COMPONENT DESCRIPTION SPECIFICATION MIN TYP MAX UNIT
L1 Boost Converter Inductor Inductance, 20% Tolerance 2.2 µH
Saturation Current 2.6 A
L2, L3 EMI Filter Inductors (optional) Impedance at 100MHz 120 Ω
DC Resistance 0.095 Ω
DC Current 1.5 A
Size 0402 EIA
C1 Boost Converter Input Capacitor Capacitance, 20% Tolerance 10 µF
C2 Boost Converter Output Capacitor Type X5R
Capacitance, 20% Tolerance 22 47 µF
Rated Voltage 16 V
Capacitance at 8.5 V derating 7 µF
C3, C4 EMI Filter Capacitors (optional, must use L2, L3 if C3, C4 used) Capacitance 1 nF

8.2.1.1 Design Requirements

Table 13. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Audio Input Digital Audio, I2S
Current and Voltage Data Stream Digital Audio, I2S
Mono or Stereo Configuration Mono
Max Output Power at 1% THD+N 3.3

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Audio Input/Output

The choice of digital or analog audio input is driven by system specific considerations. However, since a digital audio interface will typically be used to send current and voltage data from the TAS2552 to a system processor, using a bidirectional I2S interface is likely to be the best choice.

If a digital audio input is used, the analog inputs, IN+ and IN-, should be shorted together, and not tied to ground.

8.2.1.2.2 Mono/Stereo Configuration

In this application, the device is assumed to be operating in mono mode. See General I2C Operation for information on changing the I2C address of the TAS2552 to support stereo operation. Mono or stereo configuration does not impact the device performance.

8.2.1.2.3 Boost Converter Passive Devices

The boost converter requires three passive devices that are labeled L1, C1 and C2 in Figure 50 and whose specifications are provided in Table 12. These specifications are based on the design of TAS2552 and are necessary to meet the performance targets of the device. In particular, L1 should not be allowed to enter in the current saturation region.

Specifically, the product of L1 and C2 (derated value at 8.5 V) has to be greater than 10e-12 for boost stability after accounting worst case variation of L1 and C2. To satisfy sufficient energy transfer, L1 needs to be > 2 µH at the boost switching frequency (~1.75 MHz). Minimum C2 (derated value at 8.5 V) should be > 4 µF for Class-D power delivery specification. The saturation current for L1 should be > ILIM to deliver Class-D peak power.

8.2.1.2.4 EMI Passive Devices

The TAS2552 supports edge-rate control to minimize EMI, but the system designer may want to include passive devices on the Class-D output devices. These passive devices that are labeled L2, L3, C3 and C4 in Figure 50 and their recommended specifications are provided in Table 12. If C3 and C4 are used, they must be placed after L2 and L3 respectively to maintain the stability of the output stage.

8.2.1.2.5 Miscellaneous Passive Devices

  • VREG Capacitor: Needs to be 10 nF to meet boost and class-D power delivery and efficiency specs.
  • BIAS Capacitor: Needs to be 1 µF to meet PSSR and noise performance.

8.2.1.3 Application Performance Plots

TAS2552 C004_SLAS898.png
AGC=OFF, Gain = 15 dB
Figure 51. THD+N vs Output Power (8Ω) for Digital Input
TAS2552 C019_SLAS898.png
Use start-up sequence in Initialization
Figure 53. Startup Timing
TAS2552 C005_SLAS898.png
AGC=OFF, Gain = 15 dB, Pout = 1 W
Figure 52. THD+N vs Frequency (8Ω) for Digital Input
TAS2552 C020_SLAS898.png
Class D output and EN pulled low
Figure 54. Shutdown Timing

8.2.2 Typical Application - Analog Audio Input

Using the analog audio input is very similar to the digital audio input case in Typical Application - Digital Audio Input, and this section will only discuss the differences from the digital input configuration.

TAS2552 Apps_Diagram_Analog_Input.gifFigure 55. Typical Application Schematic

8.2.2.1 Design Requirements

Table 14. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Audio Input Analog
Current and Voltage Data Stream Digital Audio, I2S
Mono or Stereo Configuration Mono
Max Output Power at 1% THD+N 3.3

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Audio Input/Output

In this application, system considerations require the use of an analog audio input. Note that a digital audio interface, such as I2S, still needs to be connected to send current and voltage data from the TAS2552 to a system processor.

The analog inputs to TAS2552 should be ac-coupled to the device terminals to allow decoupling of signal source's common mode voltage with that of TAS2552's common mode voltage. The input coupling capacitor in combination with the selected input impedance of TAS2552 forms a high-pass filter.

Equation 3. Fc = 1/(2*π*RinCc)
Equation 4. Cc = 1/(2*π*RinFc)
TAS2552 TAS_schem_app_ana_in_1r_las898.gifFigure 56. Analog Input Connection

For high fidelity audio playback, it is desirable to keep the cutoff frequency of the high pass filter below the minimum reproducible frequency of the speaker. For example, a 1 µF capacitor connected to the differential analog inputs with input resistance 10 kΩ results in a cutoff frequency of 16 Hz.

8.2.2.3 Application Performance Plots

TAS2552 C006_SLAS898.png
AGC=OFF, Gain = 15 dB, f = 1 kHz
Figure 57. THD+N vs Output Power (8Ω) for Analog Input

TAS2552 C007_SLAS898.png
AGC=OFF, Gain = 15 dB
Figure 58. THD+N vs Frequency (8Ω) for Analog Input

8.2.3 Typical Application - Maximum Output Power, Analog Audio Input

This application is the same as Typical Application - Analog Audio Input, except that in this case the boost current limit is set to the maximum value of 3.1 A and the boost inductor needs to be chosen appropriately. See Configurable Boost Current Limit (ILIM) for instructions on setting the boost current limit. The same boost current limit and resulting capacitor change can be used for digital audio input as well.

For schematic, see Figure 55.

Table 15. Recommended External Components

COMPONENT DESCRIPTION SPECIFICATION MIN TYP MAX UNIT
L1 Boost Converter Inductor Inductance, 20% Tolerance 2.2 µH
Saturation Current 3.1 A
L2, L3 EMI Filter Inductors (optional) Impedance at 100MHz 120 Ω
DC Resistance 0.095 Ω
DC Current 1.5 A
Size 0402 EIA
C1 Boost Converter Input Capacitor Capacitance, 20% Tolerance 10 µF
C2 Boost Converter Output Capacitor Type X5R
Capacitance, 20% Tolerance 22 47 µF
Rated Voltage 16 V
Capacitance at 8.5 V derating 7 µF
C3, C4 EMI Filter Capacitors (optional, must use L2, L3 if C3, C4 used) Capacitance 1 nF

8.2.3.1 Design Requirements

Table 16. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Audio Input Analog
Current and Voltage Data Stream Digital Audio, I2S
Mono or Stereo Configuration Mono
Max Output Power at 1% THD+N 4.0

8.2.3.2 Detailed Design Procedure

The Design Procedure is the same as in Detailed Design Procedure.

8.2.3.3 Application Performance Plots

TAS2552 C026_SLAS898.png
AGC=OFF, Gain = 15 dB, f = 1 kHz, VBAT = 4.2 V
Figure 59. THD+N vs Output Power (8Ω) for Analog Input

8.3 Initialization

To configure the TAS2552, follow these steps.

  1. Bring-up the power supplies as in Power Supply Sequencing.
  2. Set the EN terminal to HIGH.
  3. Configure the registers in the sequence below. Do not set the bits in the final two steps to zero anytime before the end of the sequence.
    • Configure device register
    • ...
    • ...
    • ...
    • Configure device register
    • Set Register 0x0D D[7:0] = 0xC0
    • Set Register 0x0E D[5] = 1
    • Set Register 0x02 D[0] = 0
    • Set Register 0x01 D[1] = 0