JAJSC93E データシート

JAJSC93E June 2016 – December 2017 TAS2560

PRODUCTION DATA.

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）

YFF|30

サーマルパッド・メカニカル・データ

発注情報

9 Detailed Description

9.1 Overview

The TAS2560 is a low-power, high-performance boosted Class-D Audio amplifier that can be used in numerous applications. The device features an ultra low-noise audio DAC and Class-D power amplifier which incorporates speaker voltage and current sensing feedback. The TAS2560, from a 4.2 V, supply drives up to 5.6 W into a 4-Ω speaker with 1% THDN or 3.7 W into an 8-Ω speaker with 1% THDN. The TAS2560 accepts input audio data rates from 8 kHz to 96 kHz to fully support both speaker-phone and music applications. The MCLK frequency range can be from 512 kHz to 49.15 Mhz. Also supported are crystal based MCLK frequencies of 6 Mhz, 12 Mhz, 13 Mhz, and 19.2 Mhz. Left + Right Input Mixing is available when used in a mono only application.

The multi-level Class-H boost converter generates the Class-D amplifier supply rail. When the audio signal requires a output power below VBAT, the boost improves system efficiency by deactivating and connecting VBAT directly to the Class-D amplifier supply. When higher audio output power is required, the boost quickly activates and provides a much louder and much clearer signal than can be achieved in any standard amplifier speaker system design approach. A boost inductor of 1uH can be used with a slight increase in boost ripple.

On-chip Battery Guard AGC system can limit audio power levels or even shutdown the TAS2560 to avoid an undesired system reset as the supply voltage decays. The Class-D output switching frequency is synchronous with the digital input audio sample rate to avoid left and right PWM frequency differences from beating in stereo applications. PWM Edge rate control and Spread Spectrum features are available if further EMI reduction is desired in the user’s system.

The interrupt request pin, IRQ, indicates a device error condition. The interrupt flag conditions are selectable via I²C and include: thermal overload, Class-D over-current, VBAT level low, brownout, and clock error. The IRQ signal is active-high for an interrupt request and high-Z during normal operation. This behavior can be changed by a register setting to tri-state the pin during normal operation to allow the IRQ pin to be tied in parallel with other active-low interrupt request pins on other devices in the system.

Stereo configuration can be achieved with two TAS2560 devices by using the ADDR pin to set different I²C addresses in I²C mode. Refer to the General I2C Operation sections for more details.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 General I²C Operation

The TAS2560 operates as an I²C slave over the IOVDD voltage range. It is adjustable to one of four I²C addresses. This allows multiple TAS2560 devices in a system to connect to the same I²C bus. The I²C pins are fail-safe. Therefore, if the part is not powered or is in shutdown the I²C pins will not have an impact the I²C bus allowing it to remain useable.

The I²C address can then be set using the ADDR pin according to Table 1. The ADDR pin configures the two LSB bits of the following 7-bit binary address A6-A0 of 10011xx. This permits the I²C address of TAS2560 to be 0x4C(7bit) through 0x4F(7-bit). For example, if the ADDR pin is shorted to ground the TAS2560 I²C address would be 0x4C(7bit). This is equivalent to 0x98 (8-bit) for writing and 0x99 (8-bit) for reading.

Table 1. I²C Address Selection

ADDR Pin Conneciton	I²C Device Address
Short to GND	0x4C
Connection to GND using 22 kΩ Resistor	0x4D
Connection to IOVDD using 22 kΩ Resistor	0x4E
Short to IOVDD	0x4F

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The corresponding pins on the TAS2560 for the two signals are SDA and SCL. The bus transfers data serially, one bit at a time. The address and data 8-bit bytes are transferred most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 25 shows a typical sequence.

The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The device holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bi-directional bus using a wired-AND connection.

Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Use pull-up resistors between 660 Ω and 4.7 kΩ. Do not allow the SDA and SCL voltages to exceed the device digital interface supply voltage, IOVDD.

Figure 25. Typical I²C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. Figure 25 shows a generic data transfer sequence.

9.3.2 Single-Byte and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for all registers. During multiple-byte read operations, the TAS2560 responds with data, a byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledges.

The TAS2560 supports sequential I²C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I²C write transaction has taken place. For I²C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.

9.3.3 Single-Byte Write

As shown in Figure 26, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I²C device address and the read/write bit, the TAS2560 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the device internal memory address being accessed. After receiving the register byte, the device again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Figure 26. Single-Byte Write Transfer

9.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TAS2560 as shown in Figure 27. After receiving each data byte, the device responds with an acknowledge bit.

Figure 27. Multiple-Byte Write Transfer

9.3.5 Single-Byte Read

As shown in Figure 28, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. For the data-read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is set to a 0.

After receiving the TAS2560 address and the read/write bit, the device responds with an acknowledge bit. The master then sends the internal memory address byte, after which the device issues an acknowledge bit. The master device transmits another start condition followed by the TAS2560 address and the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the TAS2560 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.

Figure 28. Single-Byte Read Transfer

9.3.6 Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the TAS2560 to the master device as shown in Figure 29. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 29. Multiple-Byte Read Transfer

9.3.7 PLL

The TAS2560 on-chip PLL generates the necessary internal clock frequency for the audio DAC, I-V sensing ADCs, and DSP. The programmability of the PLL allows TAS2560 operation from a wide variety of clocks that may be available in the system application. The configurable PLL clock path is shown in Figure 30.

Figure 30. PLL_CLK Source and Generation

The PLL input supports clocks varying from 512 kHz to 20 MHz and is register programmable to enable generation of required PLL_CLK from various clocks with fine resolution. The PLL output clock PLL_CLK is determined from PLL_CLKIN using the following formula:

Equation 1. TAS2560 clock_pll_gen_eq.gif

The PLL multipliers and dividers are program using the register in Table 2. The table includes also the range of values support and the default values. The D-divider value is 14-bits wide and is controlled by 2 registers. For proper update of the D-divider value, PLL_DVAL_1 must be programmed first followed immediately by PLL_DVAL_2. Unless the write to PLL_DVAL_2 is completed, the new value of D will not take effect.

Table 2. PLL Scaling Registers

PLL Divider	Register Name	Field	Range	Default
J	PLL_JVAL[6:0]	PLL_MULT_J	1, 2, 3, … 63	4
D	PLL_DVAL_1[5:0] & PLL_DVAL_2[7:0]	PLL_MULT_D	0, 1, 2, ... 9999	0
P	PLL_CLKIN[5:0]	PLL_P_DIV	64,1,2,3, ... 63	1

Field PLL_CLK_SRC in register PLL_CLKIN configures the PLL clock input, PLL_CLKIN.

Table 3. PLL Clock Input Source

PLL_CLKIN[7:6] (PLL_CLK_SRC)	PLL_CLKIN Source
00	Input from BCLK
01	Input from MCLK (default)
10	Input from PDMLK
11	Reserved

The following conditions must be satisfied in the PLL configuration:

If D = 0 (Integer Mode), the PLL clock input (PLL_CLKIN) must satisfy:
If D > 0(Fractional Mode), the PLL clock input (PLL_CLKIN) must satisfy:
$TAS2560 clock_pll_gen_eq_fractional.gif$
The PLL output needs to be configured between 100 MHz and 200 MHz

Finally, the PLL_LOWF field in register PLL_JVAL must be configured properly based on the PLL_INPUT_CLK intermediate clock frequency.

Table 4. PLL Clock Input Source

PLL_JVAL[7] (PLL_LOWF)	PLL_INPUT_CLK Condition
0	>= 1MHz (default)
1	< 1MHz

9.3.8 Clock Distribution

TAS2560 clocking tree is driven by the PLL output. In order for this block to properly function, the output of the PLL (PLL_CLK) should be exactly 1024 times the sampling rate(Fs) or PLL_CLK=1204*Fs. For example, PLL_CLK should be 49.152 MHz for 48 kHz sampling rate or 45.1584 MHz for 44.1 kHz sampling rate. The following clocks that can be used for the audio interface clocking, see section Audio Digital I/O Interface for more information.

Table 5. Clocking Block Rates

Internal Clocking Node	Clocking Rate
NDIV_CLK	CLK_IN / 2
DAC_MOD_CLK	CLK_IN / 16
ADC_MOD_CLK	CLK_IN / 16

9.3.9 Clock Error Detection

TAS2560 has two clock error detection blocks that soft-mute the playback path when errors in the clocking signals occur. Clock error detection 1 block is used for monitoring the audio interfaces. The clock error detection 2 block is used for monitoring the internal clocks for situations where the audio interface clocks are different from the PLL input clock.

Table 6. Clock Error 1 Source

CLK_ERR_1[4] (CLK_E1_SRC)	Input Source
0	ASI_CLK (default)
1	PDM_CLK

Table 7. Clock Error 2 Source

CLK_ERR_1[3:2] (CLK_E2_SRC)	Input Source
00	DAC Modulator Clock (default)
01	ADC Modulator Clock
10	PLL Clock
11	Reserved

The clock error detection blocks may be disabled using field CLK_ERR1_EN and CLK_ERR2_EN. It is recommend to disable these blocks. Both clock error blocks must be enable or disabled together to ensure correct operation. When clock error blocks are enabled the idle channel detection used to reduce power consumption must be disabled. It is recommended to use PurePath Console 3 Software TAS2560 Application software to generate the device configuration files. The following code should be written to disable the idle channel detection block.

#add in dsp memory write section after Device power up and a delay
#assuming B0_P0
w 98 00 32 
w 98 6c 00 00 00 00 # disabling idle channel detect
w 98 00 00

Table 8. Clock Error 1 Enable

CLK_ERR_1[1] (CLK_E1_EN)	Clock Error Detection
0	disabled
1	enabled (default)

Table 9. Clock Error 2 Source

CLK_ERR_1[0] (CLK_E2_EN)	Clock Error Detection
0	disabled
1	enabled (default)

The detection block will trigger when the clock input to the specified detection block is not present within the respective specified time of field CLK_ERR1_TIME or CLK_ERR2_TIME

Table 10. Clock Error 1 Timeout

CLK_ERR_2[5:3] (CLK_E1_TIME)	Timeout
000	11 ms
001	22 ms
010	44 ms
011	87 ms
100	174 ms
101	350 ms
110	700 ms
111	1.2 s (default)

Table 11. Clock Error 2 Timeout

CLK_ERR_2[2:0] (CLK_E2_TIME)	Timeout
000	11 ms
001	22 ms
010	44 ms
011	87 ms
100	174 ms
101	350 ms
110	700 ms
111	1.2 s (default)

When a clocking error is detected the playback will be soft-mute at a rate set by field CLK_ERR_MR in register CLOCK_ERR_CFG_2. The error will be recorded in the sticky register INT_DET_1 and can be reported on the interrupt pin if mask in register INT_CFG_2

Table 12. Clock Error Soft-mute Ramp Rate

CLK_ERR_CFG_2[7:6] (CLK_ERR_MR)	Ramp-down Rate
00	15 us per dB (default)
01	30 us per dB
10	60 us per dB
11	120 us per dB

When the clock is available the system will perform a pop-free un-mute and resume operation.

9.3.10 Class-D Edge Rate Control

The edge rate of the Class-D output is controllable via I²C field EDGE_RATE in register EDGE_ISNS_BOOST. This allows users the ability to adjust the switching edge rate of the Class-D amplifier, trading off some efficiency for lower EMI. Table 13 lists the typical edge rates. The default edge rate of 14 ns passes EMI testing. The default value is recommended but may be changed if required.

Table 13. Class-D Edge Rate Control

EDGE_ISNS_BOOST[7:5] (EDGE_RATE)	t_R AND t_F (TYPICAL)
000	Reserved
001	Reserved
010	29 ns
011	25 ns
100	14 ns (default)
101	13 ns
110	12 ns
111	11 ns

9.3.11 IV Sense

The TAS2560 provides speaker voltage and current sense for real-time monitoring of loudspeaker behavior. The VSNS_P and VSNS_N pins should be connected after any ferrite bead filter (or directly to the OUT_P and OUT_N connections if no EMI filter is used). The V-Sense connections eliminate IR drop error due to packaging, PCB interconnect or ferrite bead filter resistance. The V-sense connections are also used for post filter Class-D feedback to correct for any IR-drop induced gain error or non-linearities due to the ferrite bead. It should be noted that any interconnect resistance after the V-Sense terminals will not be corrected for. Therefore, it is advised to connect the sense connections as close to the load as possible. Additionally, the v-sense pins are used the close the feedback loop on the Class-D amplifier externally. This Post-Filter Feedback (PFFB) minimized the THD introduced from the filter-beads used in the system.

Figure 31. V-Sense Connections

The I-Sense can be configured for three ranges and shown in Table 14. This should be set appropriately based on the DC resistance of the speaker. I-Sense and V-Sense can additionally be powered down as shown in Table 15 and Table 16. When powered down, the device will return null samples for the powered down sense channels.

Table 14. I-Sense Current Range

EDGE_ISNS_BOOST[4:3] (ISNS_SCALE)	Full Scale Current	Speaker Load Impedance
00	1.25 A (default)	8 Ω
01	1.5 A	6 Ω
10	1.75 A	4 Ω
11	Reserved	Reserved

Table 15. I-Sense Power Down

PWR_CTRL_1[2] (MUTE_ISNS)	Setting
0	I-Sense is active (default)
1	I-Sense is powered down

Table 16. V-Sense Power Down

PWR_CTRL_1[1] (MUTE_VSNS)	Setting
0	V-Sense is active (default)
1	V-Sense is powered down

9.3.12 Boost Control

The TAS2560 internal processing algorithm automatically enables the boost when need. A look-ahead algorithm monitors the battery voltage and the digital audio stream. When the speaker output approaches the battery voltage the boost is enabled in-time to supply the required speaker output voltage. When the boost is no longer required it is disable and bypassed to maximize efficiency. The boost can be configured in one of two modes. The first is low in-rush (Class-G) supporting only boost on-off and has the lowest in-rush current. The second is high-efficiency (Class-H) where the boost voltage level is adjusted to a value just above what is needed. This mode is more efficient but has a higher in-rush current to quickly transition the levels. This can be configured using Table 17.

Figure 32. Boost Mode Signal Tracking Example

Table 17. Boost Mode

SPK_CTRL[4] (BST_MODE)	Boost Mode
0	Class-H - High efficiency
1	Class-G - Low in-rush (default)

9.3.13 Thermal Fold-back

The TAS2560 monitors the die temperature and prevents if from going over a set limit. When enabled a internal controller will automatically adjust the signal path gain to prevent the die temperature from exceeding this limit. This allows instantaneous peak power to be delivered to the speaker while limiting the continuous power to prevent thermal shutdown. The configuration parameters for the thermal fold-back are part of the DSP core and can be set using the PurePath Console 3 Software TAS2560 Application software for the TAS2560 part under the Device Control Tab.

9.3.14 Battery Guard AGC

The TAS2560 monitors battery voltage and the audio signal to automatically decrease gain when the battery voltage is low and audio output power is high. This provides louder audio while preventing early shutdown at end-of-charge battery voltage levels. The battery tracking AGC starts to attenuate the signal once the voltage at the Class-D output exceeds V_LIM for a given battery voltage (VBAT). If the Class-D output voltage is below the V_LIM value, no attenuation occurs. If the Class-D output exceeds the V_LIM value the AGC starts to attack the signal and reduce the gain until the output is reduced to V_LIM. Once the signal returns below V_LIM plus some hysteresis the gain reduction decays. The V_LIM is constant above the user configurable inflection point. Below the inflection point the V_LIM is reduced by a user configurable slope in relation to the battery voltage. The attack time, decay time, hysteresis, inflection point and V_LIM/VBAT slope below the inflection point are user configurable. The parameters for the Battery Tracking AGC are part of the DSP core and can be set using the PurePath Console 3 Software TAS2560 Application software for the TAS2560 part under the Device Control Tab. Below a VBAT level of 2.9 V, the boost will turn on to ensure correct operation but results in increased current consumption. The device is functional until the set brownout level is reached and the device shuts down. The minimum brownout voltage is 2.7 V.

Figure 33. VLIM versus Supply Voltage (VBAT)

When the VBAT voltage drops below the brownout threshold the TAS2560 will power-down to prevent damage. The brownout can be reported on the interrupt pin. See section IRQs and Flags on how to enable this feature. Once the device voltage returns again above the brownout limit the device will need to be externally re-powered, see Brownout.

9.3.15 Configurable Boost Current Limit (ILIM)

The TAS2560 has a configurable boost current limit (ILIM). The default current limit is 3A but this limit may be set lower based on selection of passive components connected to the boost. The TAS2560 supports 4 different boost limits and can be set using Table 18.

Table 18. Current Limit Settings

EDGE_ISNS_BOOST[1:0] (BOOST_ILIM)	BOOST CURRENT LIMIT (A)
00	1.5
01	2.0
10	2.5
11	3.0 (default)

9.3.16 Fault Protection

The TAS2560 has several protection blocks to prevent damage. Those blocks including how to resume from a fault are presented in this section.

9.3.16.1 Speaker Over-Current

The TAS2560 has an integrated over-current protection that is enabled once the Class-D is powered up. A fault on the Class-D output causing a large current in the range of 3 A to 5 A triggers the over-current fault. Once the fault is detected the TAS2560 disables the audio channel and powers down the Class-D amplifier. When an over-current event occurs, a status flag INT_OVRI is set. This register is sticky and the bit remains high for as long as it is not read, or the device is not reset. The over-current event can also be used to generate an interrupt if required. Refer to IRQs and Flags for more details. To re-enable the audio channel after a fault the Class-D the device must be powered back up using field PWR_DEV, see Table 53.

9.3.16.2 Analog Under-Voltage

The TAS2560 device has an integrated undervoltage protection on the analog power supply lines VDD and VBAT. The undervoltage limit fault is triggered when VDD is less than 1.5V or VBAT is less than 2.4 V. Once the fault is detected the TAS2560 device will disable the audio channel and power down the Class-D amplifier. When an under-voltage event occurs, a status flag INT_AUV is set. This register is sticky and the bit will remain high for as long as it is not read, or the device is not reset. The undervoltage event can also be used to generate an interrupt if required. Refer to IRQs and Flags for more details. To re-enable the audio channel after a fault the Class-D the device must be powered back up using field PWR_DEV, see Table 53.

9.3.16.3 Die Over-Temperature

The TAS2560 has an integrated over temperature protection that is enabled once the Class-D is powered up. If the device internal junction temperature exceeds the safe operating region it will trigger the over-temperature fault. Once the fault is detected the TAS2560 disables the audio channel and powers down the Class-D amplifier. By default the device is set to auto-retry and will attempt to power up the class-D every 100ms. If the over-termperature condition is still present it will shut-down again. The auto-retry can be disabled by setting the register field PROT_OT_AR high. When an over-temperature event occurs, a status flag at INT_ORVT is set. This register is sticky and the bit will remain high for as long as it is not read, or the device is not reset. The over temperature event can also be used to generate an interrupt if required. Refer to IRQs and Flags section for more details. To re-enable the audio channel after a fault the Class-D the device must be powered back up using field PWR_DEV, see Table 53.

Table 19. Die Over-Temperature Auto-Retry

PROTECTION_CFG_1[2] (PROT_OT_AR)	Over Temperature Protection Auto-Retry
0	Enabled (default)
1	Disabled

9.3.16.4 Clocking Faults

The TAS2560 has two clock error detection blocks. The first is used to monitor the Audio Serial Interfaces (ASI). If a clock error is detected on the ASI interfaces audio artifacts can occur at the Class-D output. When enabled the ASI clock error detection can soft-mute the device, then shutdown the Class-D and DSP core. The second clock error detection block can monitor the internal DAC, ADC, and PLL clocks and used when the PLL clock may be from a different source than the ASI clocks. When a clock error is detected the output is soft-muted and the Class-D powered down. Information on configuring the error detection is in section Clock Error Detection

When a clocking error occurs the following sequence should be performed to restart the device.

Clear the clock error interrupts by reading the sticky flags at register INT_DET_1 fields INT_CLK1 and INT_CLK2
Clear the power error field PWR_ERR in register PWR_CTRL_2

9.3.16.5 Brownout

The TAS2560 has an integrated brownout system to shutdown the device when the battery voltage drops to an insufficient level. This user configurable level can be set under Device Control in the PurePath Console 3 Software TAS2560 Application. When brownout event occurs a status flag B0_P0_R38[3] is set. This register is sticky and the bit remains high for as long as it is not read, or the device is not reset. The brownout event can also be used to generate an interrupt if required. Refer to IRQs and Flags section for more details. Once the battery voltage drops below the defined threshold the following actions occur.

The audio playback is muted in a graceful soft-stepping manner
DSP, clock dividers, and analog blocks are powered down.
The brownout is reported in field PWR_ERR.

Once the device voltage returns again above the brownout limit the device will need to be externally re-powered by

Clear the brownout error interrupts by reading the sticky flags at register INT_DET_1 fields INT_BRNO
Clear the field PWR_ERR in register PWR_CTRL_2.

Table 20. Power Down Error

PWR_CTRL_2[0] (PWR_ERR)	Power Down
0	No error, device normal operation
1	Brownout detected, device powered down

9.3.17 Spread Spectrum vs Synchronized

The Class-D switching frequency can be selected to work in three different modes of operations selected by Table 21. This configuration needs to be done before powering up the audio channel. The first is a synchronized mode where the Class-D frequency is synchronized to audio input sample rate. This is the default mode of operation and can be used in stereo applications to avoid inter-modulation beating of the Class-D frequency from multiple chips. The Class-D switching frequency in this mode can be configured as 384 kHz or 352.8 kHz. The 384 kHz frequency is the default mode of operation, and can be used for input signals running on clock rates of 48 kHz or its sub-multiples. For input signals running on clock rate of 44.1 kHz and its sub-multiples, the switching frequency can be selected as 352.8 kHz using field RAMP_FREQ.

The second mode is fixed-frequency mode and the ramp is generated from the internal oscillator. The internal oscillators across chips will vary slightly and this can create an intermodulation beating in application where more than one TAS2560 is used.

The last mode is spread-spectrum mode and used to reduce wideband spectral content. This can improve EMI emissions radiated by the speaker by spreading out the noise in the spectrum. In this mode, the Class-D switching frequency varies +-5% or +-10% base on the Table 23 around the Table 22 around a 384 kHz center frequency. These registers should be written before powering up the audio channel.

Table 21. Ramp Clock Mode

RAMP_CTRL[7:6] (RAMP_MODE)	Setting
00	Sync Mode - ramp generated from digital audio clock (default)
01	Fixed Frequency Mode(FFM) - ramp generated from internal oscillator
10	Spread Spectrum Mode(SSM) - ramp generated from internal oscillator with spread spectrum
11	Reserved

Table 22. Ramp Clock Frequency

RAMP_CTRL[5:4] (RAMP_FREQ)	Setting
00	384 kHz - Use for Fs multiples of 48 kHz (default)
01	352.8 kHz - Use fpr Fs multiples of 44.1 kHz
10	Reserved
11	Reserved

Table 23. Ramp SSM Mode

RAMP_CTRL[1:0] (RAMP_FREQMOD)	Setting
00	Reserved
01	SSM mode enabled with ramp frequency modulated for ±5 % (default)
10	SSM mode enabled with ramp frequency modulated for ±10 %
11	Reserved

9.3.18 IRQs and Flags

Internal device flags such as over-current, under-voltage, etc can be routed to the interrupt. If more than one flag is asserted the interrupt output is the logical OR-ing of all flags. If multiple flags are asserted the host should then query the interrupts sticky register to determine which event triggered the interrupt. For example, to route the Brownout and Speaker Over Current flags to the IRQ pin the following register would be set INT_CFG_2=0x88.

Table 24. Interrupt Registers

Flag Description	Sticky Register Bit	Register to Enable Interrupt Mask
Speaker Over Current	INT_DET1[7] (INT_OVRC)	INT_CFG_2[7] (INTM_OVRC)
Speaker Over Voltage	INT_DET1[6] (INT_OVRV)	INT_CFG_2[6] (INTM_ORV)
Clock Error Detection 1	INT_DET1[5] (INT_CLK1)	INT_CFG_2[5] (INTM_CLK2)
Over Temperature	INT_DET1[4] (INT_OVRT)	INT_CFG_2[4] (INTM_OVRT)
Brownout	INT_DET1[3] (INT_BRNO)	INT_CFG_2[3] (INTM_BRNO)
Clock Error Detection 2	INT_DET1[2] (INT_CLK2)	INT_CFG_2[2] (INTM_CLK1)
Clock Halt Word Clock	INT_DET2[7] (INT_WCHLT)	INT_CFG_2[1] (INTM_WCHLT)
Clock Halt Modulator Clock	INT_DET2[6] (INT_MCHLT)	INT_CFG_2[0] (INTM_MCHLT)

The IRQ pin will be low during normal operation and indicate an interrupt with a high signal output. The output drive options of the IRQ pin are shown in Table 25 and the output can be configured to support various use cases such as external HiZ for or-ing multiple parts are directly driving the high-low output. When an IRQ event occurs the IRQ can be set to toggle or pulse, see Table 28. Additionally the IRQ pin can be disabled, used as a register controlled general purpose output, or a clock pin in PDM mode of operation. The various modes are shown in Table 26. If using the IRQ pin as a general purpose output the value can be set per Table 27.

Table 25. IRQ Pin Drive

IRQ_PIN_CFG[7:5] (IRQ_DRIVE)	Output Drive IRQ Pin
001	Drive both high and low values
010	Open Drain, low-actively driven, high-HiZ (default)
011	Open Drain, low-actively driven, high-HiZ w/ pull-up
100	Open Drain, low-HiZ w/ pull-down, high-actively driven
101-111	Reserved

Table 26. IRQ Pin Mode

IRQ_PIN_CFG[2:0] (IRQ_PIN_MODE)	IRQ Pin Mode
001	Disabled and IO buffers powered down
010	Interrupt controlled output (default)
011	Reserved
100	General purpose output
101	PDM_IN_DIV output
110-111	Reserved

Table 27. IRQ GPO Value

IRQ_PIN_CFG[4] (IRQ_GPO_VAL)	IRQ Pin GPO Value
0	low (default)
1	high

Table 28. IRQ Indicator Mode

INT_CFG_1[7:6] (IRQ_IND_CFG	IRQ Pin Indicator Mode
00	Interrupt will be only one pulse(active high) of duration 2 ms. (default)
01	Interrupt will be continuously pulsed with a duration 2ms and period 4ms until interrupt sticky flags are cleared by reading INT_DET_1 and INT_DET_2
01	Interrupt will remain high after interrupt is generated until interrupt sticky flags are cleared by reading INT_DET_1 and INT_DET_2
11	Reserved

9.3.19 CRC checksum for I²C

The TAS2560 contain logic to verify that all write operations to the device were correctly received. This can be used to detect a configuration error of the device in the event of a problem or collision on the I²C bus. On every register write other than to the book switch register(B0_P0_R127) or page switch register(B0_Px_R0) will update the 8-bit CRC checksum using the contents of the 8-bit register write data. Only register write operations will update the CRC, register read operations will not change the CRC value. The CRC checksum register CRC_CHECKSUM will return the current checksum from all previous write operations. The CRC checksum register can be write to initialize the starting value and is initially defaulted to 0x00 on a reset. The polynomial used for the CRC is 0x7 (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell delineation, (1+x^1+x^2+x^8)) Since we are using CRC, order of writes will also affect CRC.


global gChecksum # To keep track of the checksum in firmware

# Function to init the local checksum as well as that inside device
function initChecksum():
	gChecksum = 0
	i2c_write(regChecksum, 0) # regChecksum is the register number of the checksum R/W reg in device

# Function to update the local checksum
function addToChecksum(addr, data):
	if addr != regChecksum: # Checksum reg is ignored
		# Update gChecksum with data. Ignore book/page registers
		tempdata = gChecksum ^ inData
		for ( i = 0; i < 8; i++ ):
			if (( tempdata & 0x80 ) != 0 ):
				tempdata <<= 1
				tempdata ^= 0x07
			else:
				tempdata <<= 1;
			gChecksum = tempdata

# Function to compare checksums
function checkChecksum():
	return (i2c_read(regChecksum) == gChecksum)
	# Existing I2C write that does multibyte write to device

function i2c_write(addr, {data}):
	# Write the stuff to the device
		
function i2c_read(addr):
	# Read the data at device addr
	return result

# New function for verified writes
function i2c_write_checksum(addr, {data}):
	initChecksum()
	i2c_write(addr, {data})
	for word in data:
		addToChecksum(addr, word)
		addr++
	return checkChecksum()

9.3.20 PurePath™ Console 3 Software TAS2560 Application

The TAS2560 advanced features and a significant portion of the device configuration is performed using PurePath Console 3 (PPC3). The base software PPC3 is downloaded and installed from the TI website. Once installed the TAS2560 application can be download from with-in PPC3. The datasheet refers to options that can be configured using the PPC3 software tool.

9.4 Device Functional Modes

9.4.1 Audio Digital I/O Interface

Audio data is transferred between the host processor and the TAS2560 via the digital audio serial interface(ASI), or audio bus. The audio bus on this device is flexible, including left or right-justified data options, support for I²S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly. The audio bus of the TAS2560, when using PCM formatted input and/or output, can be configured for left or right-justified, I²S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits where the chip input can be left, right or L+R/2.

Table 29. ASI PCM Mode

ASI_FORMAT[4:2] (ASI_MODE)	ASI Function Mode
000	I2S Mode (default)
001	DSP Mode
010	Right-Justified Mode (RJF)
011	Left-Justified Mode (LJF)
100	Mono PCM Mode
101	DSP Time Slot Mode

Table 30. ASI PCM Input Word Length

ASI_FORMAT[1:0] (ASI_LENGTH)	Word Length
00	16 bits
01	20 bits
10	24 bits (default)
11	32 bits

Table 31. ASI PCM Channel Mode

ASI_CHANNEL[1:0] (ASI_CHAN_MODE)	Input Stereo Channel
00	Left (default)
01	Right
10	(Left + Right) / 2
11	monoPCM

In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse(DSP) or a 50% duty cycle signal(I²S). The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies. Clock sources for Master mode are described in section Clock Distribution. When the audio serial data bus is powered down while configured in master mode, the terminals associated with the interface are put into a Hi-Z output state.

Table 32. ASI WCLK Mode

ASI_CFG_1[5] (ASI_WCLKM)	WCLK Mode
0	Input - Slave Mode (default)
1	Output - Master Mode

Table 33. ASI WCLK Edge

ASI_CFG_1[3] (ASI_WCLKE)	WCLK Edge
0	As per the timing spec (default)
1	Inverted with respect to timing spec

Table 34. ASI Dividers Clock Source

ASI_DIV_SRC[1:0] (ASI_DIV_CLK_SRC)	Input Stereo Channel
00	DAC_MOD_CLK (default)
01	ADC_MOD_CLK
10	NDIV_CLK
11	Reserved

Table 35. ASI WCLK Divider Power

ASI_WDIV[7] (ASI_WDIV_P)	WCLK Divider Power
0	Powered Down (default)
1	Powered Up

Table 36. ASI WCLK Divider Ratio

ASI_WDIV[6:0] (ASI_WDIV_RATIO)	WCLK Divider Ratio
0x00	128
0x01-0x1F	Reserved
0x20	32
...	...
0x40	64 (default)
...	...
0x7F	127

The bit clock is used to clock-in and clock-out the digital audio data across the serial bus. This signal can be programmed to generate variable clock pulses by controlling the bit-clock multiply-divide factor. The number of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support the case when multiple TAS2560 devices may share the same audio bus.

Table 37. ASI BCLK Mode

ASI_CFG_1[4] (ASI_BCLKM)	BCLK Mode
0	Input - Slave Mode (default)
1	Output - Master Mode

Table 38. ASI BCLK Edge

ASI_CFG_1[2] (ASI_BCLKE)	BCLK Edge
0	As per the timing spec (default)
1	Inverted with respect to timing spec

Table 39. ASI BCLK Divider Power

ASI_BDIV[7] (ASI_WDIV_P)	BCLK Divider Power
0	Powered Down (default)
1	Powered Up

Table 40. ASI BCLK Divider Ratio

ASI_BDIV[6:0] (ASI_WDIV_RATIO)	BCLK Divider Ratio
0x00	128
0x01	1 (default)
0x02	2
...	...
0x7F	127

The TAS2560 also includes a feature to offset the position of start of data transfer with respect to the word-clock(WCLK). This offset is specified in number of bit-clocks. This can be used in cases where there is a non-zero bit-clock delay from WCLK edge or to support TDM modes of operation. The TAS2560 can place the DOUT line into a Hi-Z (tri-state) condition during all bit clocks when valid data is not being sent. TDM mode is useable with I²S, LJF, RJF, and DSP interface modes and is required for stereo applications when more than one TAS2560 part is used, see Stereo Application Example - TDM Mode. The TAS2560 also has a bus keeper circuit that can be enabled in tri-sate mode. The bus-keeper is a weak internal latch that will hold the data line state without the need for external pull-up or pull-down resistors while signal lines are in the Hi-Z or non-driven state.

Table 41. ASI OFFSET1

ASI_OFFSET_1 (ASI_OFFSET1)	BCLKs from WCLK edge for data channel
0x00	0 (default)
0x01	1
0x02	2
...	...
0xFF	255

Table 42. ASI Tri-state

ASI_CFG_1[1] (ASI_TRISTATE)	Tri-state DOUT for extra BCLK cycles after frame is complete
0	disabled (default)
1	enabled

Table 43. ASI Bus-keeper

ASI_CFG_1[0] (ASI_BUSKEEP)	Tri-state DOUT for extra BCLK cycles after frame is complete
0	disabled (default)
1	enabled

9.4.1.1 I²S Mode

In I²S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

Figure 34. Timing Diagram for I²S Mode

Figure 35. Timing Diagram for I²S Mode with ASI_OFFSET1 = 2

Figure 36. Timing Diagram for I²S Mode with ASI_OFFSET1 = 0 and Inverted Bit Clock

For I²S mode, the number of bit-clocks per channel should be greater than or equal to the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

9.4.1.2 DSP Mode

In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.

Figure 37. Timing Diagram for DSP Mode

Figure 38. Timing Diagram for DSP Mode with ASI_OFFSET1=1

Figure 39. Timing Diagram for DSP Mode with ASI_OFFSET1=0 and Inverted Bit Clock

For DSP mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

9.4.1.3 DSP Time Slot Mode

In addition the TAS2560 support DSP Time slot mode. The ASI_OFFSET_2 register allows us to place the right channel anywhere in the frame after the left channel. By utilizing Time Slot Mode, the individual left and right channels can be grouped together, as shown in Figure 40. Assuming each channel contains N bits in this example to capture the left and right of channel 1 set a value off ASI_OFFSET_1=0 and ASI_OFFSET2=M*N.

TAS2560 f3262_multi_codec_1host_1pin_tdm_2.gif

Figure 40. DSP Timing for Multiple Devices Interfaced Together, Grouped Left Channels and Right Channels

Table 44. ASI OFFSET1

ASI_OFFSET_2 (ASI_OFFSET2)	BCLKs from end of left channel data channel
0x00	0 (default)
0x01	1
0x02	2
...	...
0xFF	255

9.4.1.4 Right-Justified Mode (RJF)

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

Figure 41. Timing Diagram for Right-Justified Mode

For right-justified mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data.

9.4.1.5 Left-Justified Mode (LJF)

In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock.

Figure 42. Timing Diagram for Left-Justified Mode

Figure 43. Timing Diagram for Light-Left Mode with ASI_OFFSET1 = 1

Figure 44. Timing Diagram for Left-Justified Mode with ASI_OFFSET1 = 0 and Inverted Bit Clock

For left-justified mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data. Also, the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

9.4.1.6 Mono PCM Mode

In mono PCM mode, the rising edge of the word clock starts the data transfer of the single channel of data. Each data bit is valid on the falling edge of the bit clock.

Figure 45. Timing Diagram for Mono PCM Mode

Figure 46. Timing Diagram for Mono PCM Mode with ASI_OFFSET1=2

Figure 47. Timing Diagram for Mono PCM Mode with ASI_OFFSET1=2 and Bit Clock Inverted

For mono PCM mode, the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

9.4.1.7 Stereo Application Example - TDM Mode

Time-division multiplexing (TDM) is required for two or more devices to share a common DIN connection and a common DOUT connection. Using TDM mode, all devices transmit their DOUT data in user-specified sub-frames within one WCLK period. When one device transmits its DOUT information, the other devices place their DOUT terminals in a high impedance tri-state mode. The host processor can operate in I²S mode while the TAS2560 is running in I²S TDM mode to support sharing of the same DOUT line.

TDM mode is useable with I²S, LJF, RJF, and DSP interface modes. Refer to the respective sections for a description of how to set the TAS2560 into those modes.

Figure 48. Timing Diagram for I²S in TDM Mode with ASI_OFFSET1=2

For TDM mode, the number of bit-clocks per frame should be less than the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

Figure 49 shows how to connect two TAS2560 for a stereo application.

Figure 49. Stereo Configuration with Two TAS2560 DOUT Muxed in TDM Mode

9.4.2 PDM MODE

When the TAS2560 is running in operating Mode 3 - PCM input playback + PDM IVsense output,Mode 4 - PDM input playback only, or Mode 5 - PDM input playback + PDM IVsense output the Pulse Density Modulation (PDM) interface is used and accepts Double-Date Rate (DDR) PDM stream. In PDM mode a modulated signal is applied to DIN pin. The TAS2560 PDM can be configured in a master or slave mode of operation. In master mode operation the BCLK pin will supply a clock generated from the internal clocking block at 8 times the sampling rate(see Table 5). In master mode another clock must be supplied to drive the TAS2560 internal PLL for generation of all internal clocks. In slave mode the input clock should be supplied. The PDM clock should be 8 times the audio sampling rate (PDMCLK=8*Fs) for proper operation. When PDM input clock mode (Table 46) is set to slave mode, PDM slave mode intput clock divider power (Table 48) needs to be set to be powered up. Similarly, when PDM output clock mode (Table 47) is set to slave mode, PDM slave mode output clock divider power (Table 49) needs to be set to powered up.

The Isense and Vsense data is returned on pin DOUT as a DDR PDM stream when operating in Mode 3 - PCM input playback + PDM IVsense output or Mode 5 - PDM input playback + PDM IVsense output. In these modes the Isense data is clocked out during the rising channel and the Vsense data during the falling channel of the PDM clock. Only mono PDM input data is accepted and PDM intput data edge (Table 45) is used to select the clock edge or audio channel.

Figure 50. PDM DDR Waveform

Table 45. PDM Input Data Edge

PDM_CFG[2] (PDM_CLK_E)	PDM Data Channel
0	Rising edge (default)
1	Falling edge

Table 46. PDM Input Clock Mode

PDM_CFG[1] (PDM_CI_M)	PDM Input Clock
0	Slave - input (default)
1	Master - output

Table 47. PDM Output Clock Mode

PDM_CFG[0] (PDM_CO_M)	PDM Output Clock
0	Slave - input (default)
1	Master - output

Table 48. PDM Slave Mode Input Clock Divider Power

PDM_DIV[7] (PDM_DIV_P)	PDM Slave Mode Input Clock Divider Power
0	Powered Down (default)
1	Powered Up

Table 49. PDM Slave Mode Output Clock Divider Power

DSD_DIV[7] (PDM_DSD_P)	PDM Slave Mode Output Clock Divider Power
0	Powered Down (default)
1	Powered Up

9.5 Operational Modes

9.5.1 Hardware Shutdown

The device enters hardware shutdown mode if the RESETZ pin is asserted low. In hardware shutdown mode, the device consumes the minimum quiescent current from VDD and VBAT supplies. All registers loose state in this mode and I²C communication is disabled.

If RESETZ is asserted low while audio is playing, the device immediately stop operation and enter hardware shutdown mode. This may result in pops or clicks. It is recommend to first enter software shutdown before entering hardware shutdown.

When RESETZ is released, the device will enter software shutdown. A power up sequence such as Device Power Up and Un-mute Sequence 8Ω load with the appropriate mode selected should be executed to exist shutdown in the desired mode of operation.

9.5.2 Software Shutdown

Software shutdown mode powers down all analog blocks required to playback audio, but does not cause the device to loose register state. Software shutdown is enabled by following Mute and Device Power Down Sequence sequence.

9.5.3 Low Power Sleep

The device has a low power sleep (Table 50) mode option to reduce the power consumption on analog supply VBAT. In order to use this operating mode the VBAT supply should remain powered up when in this mode. This mode disables the Power-on Reset connected to the VBAT supply reducing current consumption.

Table 50. Low Power Sleep

LOW_PWR_MODE[7] (VBAT_POR)	Low Power Sleep Mode
0	Disabled (default)
1	Enabled - VBAT POR shutdown

9.5.4 Software Reset

The TAS2560 internal logic must be initialized to a known condition for proper device function by doing a software reset. Performing software reset after a hardware reset is mandatory for reliable device boot up. A software reset can be accomplished by asserting Table 51 bit, which is self clearing. This will restore all registers to their default values. After software reset is performed, no register read/write should be performed within 100us while initialization sequence occurs.

Table 51. Software Reset

RESET[0] (RESET)	Action
0	Don't reset (default)
1	Reset(Self clearing)

9.5.5 Device Processing Modes

The TAS2560 can be initialized into one of five modes after a. These modes have should be correctly selected based on audio input and output formats and the need for IV-sense at the speaker terminals. The advanced processing features such as Battery Guard, thermal fold-back, brownout, and boost mode can be configured using PurePath Console 3 Software TAS2560 Application.

Table 52. Device Power Mode

BOOT_MODE[3:0] (DSP_MODE)	Operating Mode
0000	Reserved
0001	Mode 1 - PCM input playback only(default)
0010	Mode 2 - PCM input playback + PCM IVsense output
0011	Mode 3 - PCM input playback + PDM IVsense output
0100	Mode 4 - PDM input playback only
0101	Mode 5 - PDM input playback + PDM IVsense output

Once the mode is selected the system is powered up using field PWR_DEV. The mode should only be selected when the device is powered down PWR_DEV = 00b. Additionally, if a system fault occurs, see Fault Protection, and the system is configured to shutdown instead of auto-retry the device will enter power state powered down (PWR_DEV=00b).

Table 53. Device Power Mode

PWR_CTRL_1[7:6] (PWR_DEV)	Device Power State
00	Powered down (default)
01	Powered up with boost
10	Powered up without boost
11	Reserved

9.5.5.1 Mode 1 - PCM input playback only

Mode 1 configures the part as a digital input only amplifier and is the lowest power mode. This mode can be used to play a known power up audio sequence before the rest of the audio system software is loaded. The mode provides fault protection, brownout protection volume control, and Class-H controller. With minimal additional configuration the Battery Guard can be enabled. The I/V sense ADC are powered down to minimize power consumption.

Figure 51. Mode 1 Processing Block Diagram

A MCLK is needed in this mode if the BCLK is less than 1MHz. If BCLK and WCLK are configured for output then MCLK is taken as the input root clock.

Table 54. Pin Use Matrix Mode 1

BCLK	WCLK	DIN	DOUT	MCLK	PDMCLK	IRQ
BCLK	WCLK	DIN	NA	MCLK	NA	IRQ

9.5.5.2 Mode 2 - PCM input playback + PCM IVsense output

Mode 2 is similar to Mode 1 except the I/V sense ADCs are powered up and the data is routed back on the L/R return channels of the ASI port. This mode can be used to return the I/V data to the host to perform computations on the speaker I/V measurements such as speaker protection.

Figure 52. Mode 2 Processing Block Diagram

A MCLK is needed in this mode if the BCLK is less than 1MHz. If BCLK and WCLK are configured for output then MCLK is also required for proper internal clocking.

Table 55. Pin Use Matrix Mode 2

BCLK	WCLK	DIN	DOUT	MCLK	PDMCLK	IRQ
BCLK	WCLK	DIN	DOUT	MCLK	NA	IRQ

9.5.5.3 Mode 2 96k

Mode 2 96k is similar to Mode 2 except battery guard, brownout, and class-H is not supported at this sampling rate.

Figure 53. Mode 2 96k Processing Block Diagram

A MCLK is needed in this mode if the BCLK is less than 1MHz. If BCLK and WCLK are configured for output then MCLK is also required for proper internal clocking.

Table 56. Pin Use Matrix Mode 2 96k

BCLK	WCLK	DIN	DOUT	MCLK	PDMCLK	IRQ
BCLK	WCLK	DIN	DOUT	MCLK	NA	IRQ

9.5.5.4 Mode 3 - PCM input playback + PDM IVsense output

Mode 3 supports I²S/TDM in playback and returns IV sense on PDM output.

Figure 54. Mode 3 Processing Block Diagram

A MCLK is needed in this mode if the BCLK or PDMCLK operating in input mode is less than 1MHz. If BCLK and PDMCLK are configured for output then MCLK is also required for proper internal clocking.

Table 57. Pin Use Matrix Mode 3

BCLK	WCLK	DIN	DOUT	MCLK	PDMCLK	IRQ
BCLK	WCLK	DIN	PDMDOUT	MCLK	PDMCLK	IRQ

9.5.5.5 Mode 4 - PDM input playback only

Mode 4 supports PDM in playback only.

Figure 55. Mode 4 Processing Block Diagram

If PDMCLK is an output or and input at a clock frequency of less than 1MHz then a separate MCLK is required to provide proper internal clocking.

Table 58. Pin Use Matrix Mode 4

BCLK	WCLK	DIN	DOUT	MCLK	PDMCLK	IRQ
PDMCLK	NA	PDMDIN	NA	MCLK	NA	IRQ

9.5.5.6 Mode 5 - PDM input playback + PDM IVsense output

Mode 5 supports PDM playback with IV sense on PDM output.

Figure 56. Mode 5 Processing Block Diagram

If either PDMCLKIN or PDMCLKOUT is an input and greater than 1MHz MCLK is not require. If both are output or less that 1MHz clock rate then a separate MCLK needs to be provided for proper internal clocking.

Table 59. Pin Use Matrix Mode 5

BCLK	WCLK	DIN	DOUT	MCLK	PDMCLK	IRQ
PDMCLKIN	NA	PDMDIN	PDMDOUT	MCLK	PDMCLKOUT	IRQ

9.6 Programming

While the below scripts are provided as configuration examples, it is recommended to use PurePath Console 3 Software TAS2560 Application software to generate the device configuration files. This software contains configuration checks to ensure proper settings are used in the device for various cases and loaded the needed fixed-function DSP patches.

9.6.1 Device Power Up and Un-mute Sequence 8Ω load

The following code example provide the correct sequence including patch to power up the device, unmute and mute, and provide a clean power-down. The PurePath Console 3 Software TAS2560 Application software will create output files with the most updated patch commands. The following is a example of powering up the part in DSP Mode 2 with proper sequencing.

Example script (Power up Mode 2 and Unmute):
#############################################################################################
i i2cstd
#mclk expected is 12.288 MHz
#configuring device registers for 8 ohm speaker load
###########################   DEVICE INIT SEQ START##############################################
w 98 00 00  #Page-0
w 98 7f 00  #Book-0
w 98 01 01  #Software reset (PAGE0_REG1) 

d 1	    #Required=50e-6  #wait time for OTP-One Time Programmable memory values to be transferred to device 

##### INIT SECTION START
w 98 49 0c
w 98 3c 33
##### INIT SECTION END

##### DSP PROG SETTING START
w 98 02 02  # operate device in dev mode 2
w 98 21 00 #disable clock error detection
w 98 08 81 # SSM enabled   
##### DSP PROG SETTING END

###########################   DEVICE INIT SEQ END ###############################################

###################	CHANNEL POWER UP	####################################################
w 98 07 41 #power up device mute class d
############################################################################################

##### DSP patch
d 10
w 98 00 32	
w 98 28 7F FB B5 00
w 98 2c 80 04 4c 00
w 98 30 7F F7 6A 00
w 98 1c 7F Ff ff ff
w 98 20 00 00 00 00
w 98 24 00 00 00 00
w 98 00 3
w 98 18 04 cc cc cc
w 98 00 00
##### DSP patch update END

w 98 07 40 #power up device unmute class d

## optional(ending the script in B0_P0)
w 98 00 00 # page 0
w 98 7f 00 # book 0
########################################

9.6.2 Device Power Up and Un-mute Sequence 4Ω or 6Ω load

The following code examples provide the correct sequence including patch to power up the device, unmute and mute, and provide a clean power-down. The PurePath Console 3 Software TAS2560 Application software will create output files with the most updated patch commands. The following sequence is a example of powering up the part in DSP Mode 2 with proper sequencing.

Example script (Power up Mode 2 and Unmute):
#############################################################################################
i i2cstd
#mclk expected is 12.288 MHz
#configuring device registers for 8 ohm speaker load
###########################   DEVICE INIT SEQ START##############################################
w 98 00 00  #Page-0
w 98 7f 00  #Book-0
w 98 01 01  #Software reset (PAGE0_REG1) 

d 1	    #Required=50e-6  #wait time for OTP-One Time Programmable memory values to be transferred to device 

##### INIT SECTION START
w 98 49 0c
w 98 3c 33
w 98 09 93 # 4-ohm load setting
#w 98 09 8B # 6-ohm load setting
##### INIT SECTION END

##### DSP PROG SETTING START
w 98 02 02  # operate device in dev mode 2
w 98 21 00 #disable clock error detection
w 98 08 81 # SSM enabled
##### DSP PROG SETTING END

###########################   DEVICE INIT SEQ END ###############################################

###################	CHANNEL POWER UP	####################################################
w 98 07 41 #power up device mute class d
############################################################################################

##### DSP patch
d 10
w 98 00 32
w 98 28 7F FB B5 00
w 98 2c 80 04 4c 00
w 98 30 7F F7 6A 00
w 98 1c 7F Ff ff ff
w 98 20 00 00 00 00
w 98 24 00 00 00 00
w 98 00 33
w 98 10 6f 5c 28 f5
w 98 14 67 ae 14 7a
w 98 20 1c 00 00 00
w 98 24 1f 0a 3d 70
w 98 28 22 14 7a e1
w 98 2c 25 1e b8 51
w 98 30 28 28 f5 c2
w 98 34 2b 33 33 33
w 98 38 2e 3d 70 a3
w 98 3c 31 47 ae 14
w 98 00 33
w 98 18 06 66 66 66
w 98 00 34
w 98 34 3a 46 74 00
w 98 38 22 f3 07 00
w 98 3c 80 77 61 00
w 98 40 22 a7 cc 00
w 98 44 3a 0c 93 00
w 98 00 00
##### DSP patch update END

w 98 07 40 #power up device unmute class d

## optional(ending the script in B0_P0)
w 98 00 00 # page 0
w 98 7f 00 # book 0
########################################

9.6.3 Mute and Device Power Down Sequence

The following code example provide the correct sequence to power down the device into software shutdown. The PurePath Console 3 Software TAS2560 Application software will create output files with these commands.

Example script (Mute / Software Shutdown):
#############################################################################################
i i2cstd

###################	CHANNEL POWER DOWN ####################################################
w 98 00 00  #Page-0
w 98 7f 00  #Book-0
###################	CHANNEL POWER UP	####################################################
w 98 07 41 #power up device mute class d
############################################################################################
w 98 01 01 # software reset

9.7 Register Map

See the General I²C Operation section for more details on addressing. Register settings should be set based on the files generated from the PPC3 GUI. Because the TAS2560 is a complex system including the internal software, changes made in the TAS2560 registers not known in the PPC3 generated configurations can result in the speaker protection not operating correctly. Changes should be made from within PurePath Console 3 Software TAS2560 Application instead of manually changing registers when possible. New configuration files can be generated from PPC3 to prevent invalid configurations.

9.7.1 Register Map Summary

9.7.1.1 Register Summary Table

Addr	Register	Description	Section
0x00	PAGE	Page Select	PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
0x01	RESET	Software Reset	RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
0x02	MODE	Mode Control	MODE (book=0x00 page=0x00 address=0x02) [reset=1h]
0x04	SPK_CTRL	Speaker Control	SPK_CTRL (book=0x00 page=0x00 address=0x04) [reset=5Fh]
0x05	PWR_CTRL_2	Power Up Control 2	PWR_CTRL_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
0x07	PWR_CTRL_1	Power Up Control 1	PWR_CTRL_1 (book=0x00 page=0x00 address=0x07) [reset=0h]
0x08	RAMP_CTRL	Class	RAMP_CTRL (book=0x00 page=0x00 address=0x08) [reset=1h]
0x09	EDGE_ISNS_BOOST	Edge Rate, Isense Scale, Boost limit	EDGE_ISNS_BOOST (book=0x00 page=0x00 address=0x09) [reset=83h]
0x0F	PLL_CLKIN	PLL Clock Input Control	PLL_CLKIN (book=0x00 page=0x00 address=0x0F) [reset=41h]
0x10	PLL_JVAL	PLL J Multiplier Control	PLL_JVAL (book=0x00 page=0x00 address=0x10) [reset=4h]
0x11	PLL_DVAL_1	PLL Fractional Multiplier D Val MSB	PLL_DVAL_1 (book=0x00 page=0x00 address=0x11) [reset=0h]
0x12	PLL_DVAL_2	PLL Fractional Multiplier D Val LSB	PLL_DVAL_2 (book=0x00 page=0x00 address=0x12) [reset=0h]
0x14	ASI_FORMAT	ASI Mode Control	ASI_FORMAT (book=0x00 page=0x00 address=0x14) [reset=2h]
0x15	ASI_CHANNEL	ASI Channel Control	ASI_CHANNEL (book=0x00 page=0x00 address=0x15) [reset=0h]
0x16	ASI_OFFSET_1	ASI Offset	ASI_OFFSET_1 (book=0x00 page=0x00 address=0x16) [reset=0h]
0x17	ASI_OFFSET_2	ASI Offset Second Slot	ASI_OFFSET_2 (book=0x00 page=0x00 address=0x17) [reset=0h]
0x18	ASI_CFG_1	ASI Configuration	ASI_CFG_1 (book=0x00 page=0x00 address=0x18) [reset=0h]
0x19	ASI_DIV_SRC	ASI BDIV Clock Input	ASI_DIV_SRC (book=0x00 page=0x00 address=0x19) [reset=0h]
0x1A	ASI_BDIV	ASI BDIV Configuration	ASI_BDIV (book=0x00 page=0x00 address=0x1A) [reset=1h]
0x1B	ASI_WDIV	ASI WDIV Configuration	ASI_WDIV (book=0x00 page=0x00 address=0x1B) [reset=40h]
0x1C	PDM_CFG	PDM Configuration	PDM_CFG (book=0x00 page=0x00 address=0x1C) [reset=0h]
0x1D	PDM_DIV	PDM Divider Configuration	PDM_DIV (book=0x00 page=0x00 address=0x1D) [reset=8h]
0x1E	DSD_DIV	DSD Divider Configuration	DSD_DIV (book=0x00 page=0x00 address=0x1E) [reset=8h]
0x21	CLK_ERR_1	Clock Error and DSP memory Reload	CLK_ERR_1 (book=0x00 page=0x00 address=0x21) [reset=3h]
0x22	CLK_ERR_2	Clock Error Configuration	CLK_ERR_2 (book=0x00 page=0x00 address=0x22) [reset=3Fh]
0x23	IRQ_PIN_CFG	Interrupt Pin Configuration	IRQ_PIN_CFG (book=0x00 page=0x00 address=0x23) [reset=21h]
0x24	INT_CFG_1	Interrupt Configuration 1	INT_CFG_1 (book=0x00 page=0x00 address=0x24) [reset=0h]
0x25	INT_CFG_2	Interrupt Configuration 2	INT_CFG_2 (book=0x00 page=0x00 address=0x25) [reset=0h]
0x26	INT_DET_1	Interrupt Detected 1	INT_DET_1 (book=0x00 page=0x00 address=0x26) [reset=0h]
0x27	INT_DET_2	Interrupt Detected 2	INT_DET_2 (book=0x00 page=0x00 address=0x27) [reset=0h]
0x2A	STATUS_POWER	Status Block Power	STATUS_POWER (book=0x00 page=0x00 address=0x2A) [reset=0h]
0x2D	SAR_VBAT_MSB	SAR VBAT Measurement MSB	SAR_VBAT_MSB (book=0x00 page=0x00 address=0x2D) [reset=C0h]
0x2E	SAR_VBAT_LSB	SAR VBAT Measurement LSB	SAR_VBAT_LSB (book=0x00 page=0x00 address=0x2E) [reset=0h]
0x31	DIE_TEMP_SENSOR	Die Temperature Sensor	DIE_TEMP_SENSOR (book=0x00 page=0x00 address=0x31) [reset=0h]
0x35	LOW_PWR_MODE	Low Power Configuration	LOW_PWR_MODE (book=0x00 page=0x00 address=0x35) [reset=0h]
0x36	PCM_RATE	PCM Sample Rate	PCM_RATE (book=0x00 page=0x00 address=0x36) [reset=32h]
0x4F	CLOCK_ERR_CFG_1	Clock Error Configuration 1	CLOCK_ERR_CFG_1 (book=0x00 page=0x00 address=0x4F) [reset=0h]
0x50	CLOCK_ERR_CFG_2	Clock Error Configuration 2	CLOCK_ERR_CFG_2 (book=0x00 page=0x00 address=0x50) [reset=11h]
0x58	PROTECTION_CFG_1	Class	PROTECTION_CFG_1 (book=0x00 page=0x00 address=0x58) [reset=3h]
0x7E	CRC_CHECKSUM	Checksum	CRC_CHECKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
0x7F	BOOK	Book Selection	BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]

9.7.2 PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]

Selects the page for the next read or write.

Figure 57. PAGE Register Address: 0x00

7	6	5	4	3	2	1	0
PAGE[7:0]
RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 60. Page Select Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PAGE[7:0]	RW	0h	Selects the Register Page for the next read or write command

9.7.3 RESET (book=0x00 page=0x00 address=0x01) [reset=0h]

Controls the software reset

Figure 58. RESET Register Address: 0x01

7	6	5	4	3	2	1	0
Reserved							RESET
R-0h							RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 61. Software Reset Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R	0h	Reserved
0	RESET	RW	0h	0 = Don't care 1 = Self clearing software reset

9.7.4 MODE (book=0x00 page=0x00 address=0x02) [reset=1h]

Controls the mode of the part

Figure 59. MODE Register Address: 0x02

7	6	5	4	3	2	1	0
AUTOPAGE	Reserved				DSP_MODE[2:0]
RW-0h	RW-0h				RW-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 62. Mode Control Field Descriptions

Bit	Field	Type	Reset	Description
7	AUTOPAGE	RW	0h	0 Enable page auto increment for memory mapped registers 1 Self clearing software reset
6-3	Reserved	RW	0h	Reserved
2-0	DSP_MODE[2:0]	RW	1h	0 = Reserved 1 = PCM input playback only 2 = PCM input playback + PCM IV out 3 = PCM input playback + PDM IV out 4 = PDM input playback only 5 = PDM input playback + PDM IV out 6 = Reserved

9.7.5 SPK_CTRL (book=0x00 page=0x00 address=0x04) [reset=5Fh]

Configure the boost mode and DAC gain

Figure 60. SPK_CTRL Register Address: 0x04

7	6	5	4	3	2	1	0
BST_OFFDLY[1:0]		BST_PRE	BST_MODE	DAC_GAIN[3:0]
RW-1h		RW-0h	RW-1h	RW-Fh

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 63. Speaker Control Field Descriptions

Bit	Field	Type	Reset	Description
7-6	BST_OFFDLY[1:0]	RW	1h	0 = Reserved 1 = Reserved 2 = Reserved
5	BST_PRE	RW	0h	0 = Reserved
4	BST_MODE	RW	1h	0 = Class H - multi-level boost mode. In this mode the boost voltage will track the signal. It will result in higher inrush current from VBATT. 1 = Class -G boost mode. When the boost is needed it will turn on to the maximum boost voltage.
3-0	DAC_GAIN[3:0]	RW	Fh	DAC gain is 0 = 0db 1 = 1db 2 = 2db ... 14 = 14db 15 = 15db

9.7.6 PWR_CTRL_2 (book=0x00 page=0x00 address=0x05) [reset=0h]

This register controls device power up

Figure 61. PWR_CTRL_2 Register Address: 0x05

7	6	5	4	3	2	1	0
Reserved	Reserved	Reserved	Reserved	Reserved	Reserved		PWR_ERR
RW-0h	RW-0h	RW-0h	RW-0h	RW-0h	RW-0h		RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 64. Power Up Control 2 Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	RW	0h	Reserved
6	Reserved	RW	0h	Reserved
5	Reserved	RW	0h	Reserved
4	Reserved	RW	0h	Reserved
3	Reserved	RW	0h	Reserved
2-1	Reserved	RW	0h	Reserved
0	PWR_ERR	RW	0h	Reserved 0 = No error condition 1 = Error condition detected

9.7.7 PWR_CTRL_1 (book=0x00 page=0x00 address=0x07) [reset=0h]

This register controls device power up

Figure 62. PWR_CTRL_1 Register Address: 0x07

7	6	5	4	3	2	1	0
PWR_DEV[1:0]		Reserved	Reserved	Reserved	MUTE_ISNS	MUTE_VSNS	MUTE_AUDIO
RW-0h		RW-0h	RW-0h	RW-0h	RW-0h	RW-0h	RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 65. Power Up Control 1 Field Descriptions

Bit	Field	Type	Reset	Description
7-6	PWR_DEV[1:0]	RW	0h	Controls the device power state. If a fault is detected that powers the device down the state will be reflected in this register. 0 = Device is powered down 1 = Power up device with boost 2 = Power up device without boost 3 = Reserved
5	Reserved	RW	0h	Reserved
4	Reserved	RW	0h	Reserved
3	Reserved	RW	0h	Reserved
2	MUTE_ISNS	RW	0h	Isense is 0 = Unmuted 1 = Muted
1	MUTE_VSNS	RW	0h	Vsense D is 0 = Unmuted 1 = Muted
0	MUTE_AUDIO	RW	0h	Audio playback (pop-free) is 0 = Unmuted 1 = Muted

9.7.8 RAMP_CTRL (book=0x00 page=0x00 address=0x08) [reset=1h]

D Ramp Control

Figure 63. RAMP_CTRL Register Address: 0x08

7	6	5	4	3	2	1	0
RAMP_MODE[1:0]		RAMP_FREQ[1:0]		Reserved		RAMP_FREQMOD[1:0]
RW-0h		RW-0h		RW-0h		RW-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 66. Class Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RAMP_MODE[1:0]	RW	0h	The Class-D ramp clock mode 0 = SYNC, generated from digital audio stream 1 = FFM, generated from internal oscillator 2 = SSM, generated from internal oscillator with spread-spectrum 3 = Reserved
5-4	RAMP_FREQ[1:0]	RW	0h	The ramp frequency is 0 = 348kHz (Use for Fs=48ksps and multiples) 1 = 352.8kHz (Use for Fs=44.1ksps and multiples) 2 = Reserved
3-2	Reserved	RW	0h	Reserved
1-0	RAMP_FREQMOD[1:0]	RW	0h	Sets the ramp frequency modulation rate or to a fixed offset. 0 = Reserved 1 = Set the SSM to 5% frequency modulation 2 = Set the SSM to 10% frequency modulation 3 = Reserved

9.7.9 EDGE_ISNS_BOOST (book=0x00 page=0x00 address=0x09) [reset=83h]

Controls edge rate, sense, and boost limits

Figure 64. EDGE_ISNS_BOOST Register Address: 0x09

7	6	5	4	3	2	1	0
EDGE_RATE[2:0]			ISNS_SCALE[1:0]		Reserved	BOOST_ILIM[1:0]
RW-4h			RW-0h		RW-0h	RW-3h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 67. Edge Rate, Isense Scale, Boost limit Field Descriptions

Bit	Field	Type	Reset	Description
7-5	EDGE_RATE[2:0]	RW	4h	Set the Class-D output edge rate control to 0 = Reserved 1 = Reserved 2 = 29ns 3 = 25ns 4 = 14ns 5 = 13ns 6 = 12ns 7 = 11ns
4-3	ISNS_SCALE[1:0]	RW	0h	Sets the full-scale value of Isense channel. Should be changed based on the speaker DC impedance R0. 0 = 8ohm, Isense full-scale = 1.25A 1 = 6ohm, Isense full-scale = 1.5A 2 = 4ohm, Isense full-scale = 1.75A 3 = Reserved
2	Reserved	RW	0h	Reserved
1-0	BOOST_ILIM[1:0]	RW	3h	Sets the boost current limit to 0 = 1.5A 1 = 2A 2 = 2.5A 3 = 3A

9.7.10 PLL_CLKIN (book=0x00 page=0x00 address=0x0F) [reset=41h]

PLL Clock Input Control

Figure 65. PLL_CLKIN Register Address: 0x0F

7	6	5	4	3	2	1	0
PLL_CLK_SRC[1:0]		PLL_P_DIV[5:0]
RW-1h		RW-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 68. PLL Clock Input Control Field Descriptions

Bit	Field	Type	Reset	Description
7-6	PLL_CLK_SRC[1:0]	RW	1h	PLL Clock Input Source. PLL CLKIN is from 0 = BCLK 1 = MCLK 2 = PDMCLK
5-0	PLL_P_DIV[5:0]	RW	1h	The PLL_CLKIN divider ration that generated the input clock for the PLL P-divider is 0 = 64 1 = 1 2 = 2 ... 62 = 62 63 = 63

9.7.11 PLL_JVAL (book=0x00 page=0x00 address=0x10) [reset=4h]

PLL J Multiplier Control

Figure 66. PLL_JVAL Register Address: 0x10

7	6	5	4	3	2	1	0
PLL_LOWF	PLL_MULT_J[6:0]
RW-0h	RW-4h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 69. PLL J Multiplier Control Field Descriptions

Bit	Field	Type	Reset	Description
7	PLL_LOWF	RW	0h	This value should be set based on the output frequency of the PLL CLK_DIV register. It should be set based on this frequency being equal to and greater than 1MHz or less than 1 MHz 0 = If the PLL_CLKIN is equal to or greater than 1MHz 1 = If the PLL_CLKIN is less than 1MHz
6-0	PLL_MULT_J[6:0]	RW	4h	The PLL Multiplier J is 0 = Reserved 1 = 1 2 = 2 ... 62 = 62 63 = 63

9.7.12 PLL_DVAL_1 (book=0x00 page=0x00 address=0x11) [reset=0h]

PLL Fractional Multiplier D Val MSB

Figure 67. PLL_DVAL_1 Register Address: 0x11

7	6	5	4	3	2	1	0
Reserved		PLL_MULT_D[13:8]
RW-0h		RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 70. PLL Fractional Multiplier D Val MSB Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	RW	0h	Reserved
5--8	PLL_MULT_D[13:0]	RW	0h	PLL Fractional Multiplier D[13:8] value bits

9.7.13 PLL_DVAL_2 (book=0x00 page=0x00 address=0x12) [reset=0h]

PLL Fractional Multiplier D Val LSB

Figure 68. PLL_DVAL_2 Register Address: 0x12

7	6	5	4	3	2	1	0
PLL_MULT_D[7:0]
RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 71. PLL Fractional Multiplier D Val LSB Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PLL_MULT_D[7:0]	RW	0h	PLL Fractional Multiplier D[7:0] value bits

9.7.14 ASI_FORMAT (book=0x00 page=0x00 address=0x14) [reset=2h]

Configures the Audio Serial Interface mode and word length

Figure 69. ASI_FORMAT Register Address: 0x14

7	6	5	4	3	2	1	0
Reserved			ASI_MODE[2:0]			ASI_LENGTH[1:0]
RW-0h			RW-0h			RW-2h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 72. ASI Mode Control Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	RW	0h	Reserved
4-2	ASI_MODE[2:0]	RW	0h	The ASI Input mode format is set to 0 = I2S 1 = DSP 2 = RJF , For non-zero values of ASI_OFFSET1, LJF is preferred 3 = LJF 4 = MonoPCM 5 = TDM (DSP timeslot) 6-15 = Reserved
1-0	ASI_LENGTH[1:0]	RW	2h	Sets the ASI input word-length to 0 = 16bits 1 = 20bits 2 = 24bits 3 = 32bits

9.7.15 ASI_CHANNEL (book=0x00 page=0x00 address=0x15) [reset=0h]

Configures the Audio Serial Interface channel modes

Figure 70. ASI_CHANNEL Register Address: 0x15

7	6	5	4	3	2	1	0
Reserved				Reserved		ASI_CHAN_MODE[1:0]
RW-0h				RW-0h		RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 73. ASI Channel Control Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Reserved	RW	0h	Reserved
3-2	Reserved	RW	0h	Reserved
1-0	ASI_CHAN_MODE[1:0]	RW	0h	Configures the ASI input stereo channel mode. Do no change this register for PDM input modes. ASI input playback is 0 = Left Channel 1 = Right Channel 2 = (Left + Right) / 2 3 = monoPCM

9.7.16 ASI_OFFSET_1 (book=0x00 page=0x00 address=0x16) [reset=0h]

Configures the ASI input offset. Offset is measured with respect to WCLK

Figure 71. ASI_OFFSET_1 Register Address: 0x16

7	6	5	4	3	2	1	0
ASI_OFFSET1[7:0]
RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 74. ASI Offset Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ASI_OFFSET1[7:0]	RW	0h	ASI_OFFSET1[7:0]

9.7.17 ASI_OFFSET_2 (book=0x00 page=0x00 address=0x17) [reset=0h]

Configures the right channel offset from the left channel slot in DSP Timeslot mode

Figure 72. ASI_OFFSET_2 Register Address: 0x17

7	6	5	4	3	2	1	0
ASI_OFFSET2[7:0]
RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 75. ASI Offset Second Slot Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ASI_OFFSET2[7:0]	RW	0h	ASI_OFFSET2[7:0]

9.7.18 ASI_CFG_1 (book=0x00 page=0x00 address=0x18) [reset=0h]

Configure various ASI options

Figure 73. ASI_CFG_1 Register Address: 0x18

7	6	5	4	3	2	1	0
Reserved	Reserved	ASI_WCLKM	ASI_BCLKM	ASI_WCLKE	ASI_BCLKE	ASI_TRISTATE	ASI_BUSKEEP
RW-0h	RW-0h	RW-0h	RW-0h	RW-0h	RW-0h	RW-0h	RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 76. ASI Configuration Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	RW	0h	Reserved
6	Reserved	RW	0h	Reserved
5	ASI_WCLKM	RW	0h	Configure the ASI WCLK direction 0 = Input 1 = Output
4	ASI_BCLKM	RW	0h	Configure the ASI BCLK direction 0 = Input 1 = Output
3	ASI_WCLKE	RW	0h	Configure the WCLK to be 0 = As per the timing Protocol 1 = Inverted with respect to the timing protocol
2	ASI_BCLKE	RW	0h	Configure the BCLK to be 0 = As per the timing Protocol 1 = Inverted with respect to the timing protocol
1	ASI_TRISTATE	RW	0h	Tri-stating of DOUT for the extra ASI_BCLK cycles after Data Transfer is over for a frame is 0 = Disabled 1 = Enabled
0	ASI_BUSKEEP	RW	0h	DOUT Bus-keeper is 0 = Disabled 1 = Enabled

9.7.19 ASI_DIV_SRC (book=0x00 page=0x00 address=0x19) [reset=0h]

ASI BDIV Clock Input

Figure 74. ASI_DIV_SRC Register Address: 0x19

7	6	5	4	3	2	1	0
Reserved						ASI_DIV_CLK_SRC[1:0]
RW-0h						RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 77. ASI BDIV Clock Input Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	RW	0h	Reserved
1-0	ASI_DIV_CLK_SRC[1:0]	RW	0h	Selects the ASI_CLKIN source for BDIV and WDIV is 0 = DAC_MOD_CLK 1 = ADC_MOD_CLK 2 = NDIV_CLK 3 = Reserved

9.7.20 ASI_BDIV (book=0x00 page=0x00 address=0x1A) [reset=1h]

ASI BDIV Configuration

Figure 75. ASI_BDIV Register Address: 0x1A

7	6	5	4	3	2	1	0
ASI_BDIV_P	ASI_BDIV_RATIO[6:0]
RW-0h	RW-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 78. ASI BDIV Configuration Field Descriptions

Bit	Field	Type	Reset	Description
7	ASI_BDIV_P	RW	0h	ASI BDIV divider is 0 = Powered down 1 = Powered up
6-0	ASI_BDIV_RATIO[6:0]	RW	1h	The ASI_BDIV ration is 0 = 128 1-31 = Reserved 32 = 32 33 = 33 ... 126 = 126 127 = 127

9.7.21 ASI_WDIV (book=0x00 page=0x00 address=0x1B) [reset=40h]

ASI WDIV Configuration

Figure 76. ASI_WDIV Register Address: 0x1B

7	6	5	4	3	2	1	0
ASI_WDIV_P	ASI_WDIV_RATIO[6:0]
RW-0h	RW-40h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 79. ASI WDIV Configuration Field Descriptions

Bit	Field	Type	Reset	Description
7	ASI_WDIV_P	RW	0h	ASI WDIV divider is 0 = Powered down 1 = Powered up
6-0	ASI_WDIV_RATIO[6:0]	RW	40h	The ASI_WDIV ration is 0 = 128 1-31 = Reserved 32 = 32 33 = 33 ... 126 = 126 127 = 127

9.7.22 PDM_CFG (book=0x00 page=0x00 address=0x1C) [reset=0h]

PDM Configuration

Figure 77. PDM_CFG Register Address: 0x1C

7	6	5	4	3	2	1	0
Reserved			Reserved		PDM_CLK_E	PDM_CI_M	PDM_CIO_M
RW-0h			RW-0h		RW-0h	RW-0h	RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 80. PDM Configuration Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	RW	0h	Reserved
4-3	Reserved	RW	0h	Reserved
2	PDM_CLK_E	RW	0h	Data is latch on the following edge of the PDM clock 0 = Rising 1 = Falling
1	PDM_CI_M	RW	0h	PDM_IN_CLK direction is 0 = input 1 = output
0	PDM_CIO_M	RW	0h	PDM_OUT_CLK direction is 0 = input 1 = output

9.7.23 PDM_DIV (book=0x00 page=0x00 address=0x1D) [reset=8h]

PDM Divider Configuration

Figure 78. PDM_DIV Register Address: 0x1D

7	6	5	4	3	2	1	0
PDM_DIV_P	Reserved
RW-0h	RW-8h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 81. PDM Divider Configuration Field Descriptions

Bit	Field	Type	Reset	Description
7	PDM_DIV_P	RW	0h	PDM_IN_DIV divider is 0 = Powered down 1 = Powered up
6-0	Reserved	RW	8h	Reserved

9.7.24 DSD_DIV (book=0x00 page=0x00 address=0x1E) [reset=8h]

DSD Divider Configuration

Figure 79. DSD_DIV Register Address: 0x1E

7	6	5	4	3	2	1	0
DSD_DIV_P	Reserved	Reserved
RW-0h	RW-0h	RW-8h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 82. DSD Divider Configuration Field Descriptions

Bit	Field	Type	Reset	Description
7	DSD_DIV_P	RW	0h	DSD_DIV divider is 0 = Powered down 1 = Powered up
6	Reserved	RW	0h	Reserved
5-0	Reserved	RW	8h	Reserved

9.7.25 CLK_ERR_1 (book=0x00 page=0x00 address=0x21) [reset=3h]

Clock Error and DSP memory Reload

Figure 80. CLK_ERR_1 Register Address: 0x21

7	6	5	4	3	2	1	0
DSP_MEMRST	Reserved	Reserved	CLK_E1_SRC	CLK_E2_SRC[1:0]		CLK_E1_EN	CLK_E2_EN
RW-0h	RW-0h	RW-0h	RW-0h	RW-0h		RW-1h	RW-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 83. Clock Error and DSP memory Reload Field Descriptions

Bit	Field	Type	Reset	Description
7	DSP_MEMRST	RW	0h	Determine if the DSP memory locations will be reloaded for reasons other than user power down such as clock-halt, brownout, over current, over temp, and over voltage. 0 = Do not reload on restart 1 = Reload defaults on restart
6	Reserved	RW	0h	Reserved
5	Reserved	RW	0h	Reserved
4	CLK_E1_SRC	RW	0h	Clock error detection 1 block input is from 0 = ASI_CLK 1 = PDM_CLK
3-2	CLK_E2_SRC[1:0]	RW	0h	Clock error detection 2 block input is from 0 = DAC Modulator Clock 1 = ADC Modulator Clock 2 = PLL Clock 3 = Reserved
1	CLK_E1_EN	RW	0h	Clock error detection block 1 is 0 = Disabled 1 = Enabled
0	CLK_E2_EN	RW	0h	Clock error detection block 2 is 0 = Disabled 1 = Enabled

9.7.26 CLK_ERR_2 (book=0x00 page=0x00 address=0x22) [reset=3Fh]

Sets the clock error timeouts for detecting missing clocks

Figure 81. CLK_ERR_2 Register Address: 0x22

7	6	5	4	3	2	1	0
Reserved	Reserved	CLK_E1_TIME[2:0]			CLK_E2_TIME[2:0]
RW-0h	RW-0h	RW-7h			RW-7h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 84. Clock Error Configuration Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	RW	0h	Reserved
6	Reserved	RW	0h	Reserved
5-3	CLK_E1_TIME[2:0]	RW	0h	The chip will shutdown with a clock error 1 is the clock input to the error 1 detection block is not present for the specified time. B0_P0_R5[0] will be set to high and must be cleared before repowering the device. The clock missing time is 0 = 11ms 1 = 22ms 2 = 44ms 3 = 87ms 4 = 174ms 5 = 350ms 6 = 700ms 7 = 1.2s
2-0	CLK_E2_TIME[2:0]	RW	7h	The chip will shutdown with a clock error 1 is the clock input to the error 1 detection block is not present for the specified time. B0_P0_R5[0] will be set to high and must be cleared before repowering the device. The clock missing time is 0 = 11ms 1 = 22ms 2 = 44ms 3 = 87ms 4 = 174ms 5 = 350ms 6 = 700ms 7 = 1.2s

9.7.27 IRQ_PIN_CFG (book=0x00 page=0x00 address=0x23) [reset=21h]

Sets the interrupt pin mode of operation

Figure 82. IRQ_PIN_CFG Register Address: 0x23

7	6	5	4	3	2	1	0
IRQ_DRIVE[2:0]			IRQ_GPO_VAL	Reserved	IRQ_PIN_MODE[2:0]
RW-1h			RW-0h	RW-0h	RW-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 85. Interrupt Pin Configuration Field Descriptions

Bit	Field	Type	Reset	Description
7-5	IRQ_DRIVE[2:0]	RW	1h	Sets the output drive mode of the IRQ interrupt pin to 0 = Drive both high and low values 1 = Open Drain, low-actively driven, high-HiZ 2 = Open Drain, low-HiZ, high-actively drive 3 = Open Drain, low-actively driven, high-HiZ w/ pull-up 4 = Open Drain, low-HiZ w/ pull-down, high-actively driven 5 = Reserved Others = Reserved
4	IRQ_GPO_VAL	RW	0h	When B0_P0_R35[2:0]=b011 this is used set the value of the IRQ pin 0 = low 1 = high
3	Reserved	RW	0h	Reserved
2-0	IRQ_PIN_MODE[2:0]	RW	1h	Configures the IRQ pin mode of operation. IRQ pin is 0 = Disabled and IO buffers powered down 1 = Interrupt controlled output 2 = Reserved 3 = General purpose output 4 = PDM_IN_DIV output 5 = Reserved Others = Reserved

9.7.28 INT_CFG_1 (book=0x00 page=0x00 address=0x24) [reset=0h]

Sets the interrupt pin toggle behavior and the interrupt mask flags

Figure 83. INT_CFG_1 Register Address: 0x24

7	6	5	4	3	2	1	0
IRQ_IND_CFG[1:0]		Reserved				Reserved	Reserved
RW-0h		RW-0h				RW-0h	RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 86. Interrupt Configuration 1 Field Descriptions

Bit	Field	Type	Reset	Description
7-6	IRQ_IND_CFG[1:0]	RW	0h	Configures the interrupt indication mode and determines how the IRQ pin will indicate the interrupt. 0 = Interrupt will be only one pulse(active high) of duration 2ms. 1 = Interrupt will be multiple pulses(active high) of duration 2ms and period 4ms until interrupt sticky flags are cleared by reading INT_DET_1 and INT_DET_2 2 = Interrupt will remain high after interrupt is generated until interrupt sticky flags are cleared by reading INT_DET_1 and INT_DET_2
5-2	Reserved	RW	0h	Reserved
1	Reserved	RW	0h	Reserved
0	Reserved	RW	0h	Reserved

9.7.29 INT_CFG_2 (book=0x00 page=0x00 address=0x25) [reset=0h]

Sets the interrupt mask flags.

Figure 84. INT_CFG_2 Register Address: 0x25

7	6	5	4	3	2	1	0
INTM_OVRI	INTM_AUV	INTM_CLK2	INTM_OVRT	INTM_BRNO	INTM_CLK1	INTM_MCHLT	INT_WCHLT
RW-0h	RW-0h	RW-0h	RW-0h	RW-0h	RW-0h	RW-0h	RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 87. Interrupt Configuration 2 Field Descriptions

Bit	Field	Type	Reset	Description
7	INTM_OVRI	RW	0h	Sets the interrupt mask flag for the speaker over current detected to 0 = Clear (not used) 1 = Set (used)
6	INTM_AUV	RW	0h	Sets the interrupt mask flag for the analog under voltage detected to 0 = Clear (not used) 1 = Set (used)
5	INTM_CLK2	RW	0h	Sets the interrupt mask flag for the clock error 2 detected to 0 = Clear (not used) 1 = Set (used)
4	INTM_OVRT	RW	0h	Sets the interrupt mask flag for the die over-temperature detected to 0 = Clear (not used) 1 = Set (used)
3	INTM_BRNO	RW	0h	Sets the interrupt mask flag for the brownout detected to 0 = Clear (not used) 1 = Set (used)
2	INTM_CLK1	RW	0h	Sets the interrupt mask flag for the clock error 1 detected to 0 = Clear (not used) 1 = Set (used)
1	INTM_MCHLT	RW	0h	Sets the interrupt mask flag for the modulator clock halt detected to 0 = Clear (not used) 1 = Set (used)
0	INT_WCHLT	RW	0h	Sets the interrupt mask flag for the WCLK clock halt detected to 0 = Clear (not used) 1 = Set (used)

9.7.30 INT_DET_1 (book=0x00 page=0x00 address=0x26) [reset=0h]

Sticky register used to indicate the source of an interrupt trigger. Register is cleared once read.

Figure 85. INT_DET_1 Register Address: 0x26

7	6	5	4	3	2	1	0
INT_OVRI	INT_AUV	INT_CLK1	INT_OVRT	INT_BRNO	INT_CLK2	INT_SAR	Reserved
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 88. Interrupt Detected 1 Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_OVRI	R	0h	Sticky bit indicating that speaker over current condition 0 = did not occurred since last read 1 = occurred since last read
6	INT_AUV	R	0h	Sticky bit indicating that analog under voltage condition 0 = did not occurred since last read 1 = occurred since last read
5	INT_CLK1	R	0h	Sticky bit indicating that clock error 1 condition 0 = did not occurred since last read 1 = occurred since last read
4	INT_OVRT	R	0h	Sticky bit indicating that die over-temperature condition 0 = did not occurred since last read 1 = occurred since last read
3	INT_BRNO	R	0h	Sticky bit indicating that brownout condition 0 = did not occurred since last read 1 = occurred since last read
2	INT_CLK2	R	0h	Sticky bit indicating that the clock error 2 condition 0 = did not occurred since last read 1 = occurred since last read
1	INT_SAR	R	0h	Sticky bit indicating that the SAR complete condition 0 = did not occurred since last read 1 = occurred since last read
0	Reserved	R	0h	Reserved

9.7.31 INT_DET_2 (book=0x00 page=0x00 address=0x27) [reset=0h]

Sticky register used to indicate the source of an interrupt trigger

Figure 86. INT_DET_2 Register Address: 0x27

7	6	5	4	3	2	1	0
INT_WCHLT	INT_MCHLT	Reserved				Reserved	Reserved
R-0h	R-0h	R-0h				R-0h	R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 89. Interrupt Detected 2 Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_WCHLT	R	0h	Sticky bit indicating that WCLK clock halt condition 0 = did not occurred since last read 1 = occurred since last read
6	INT_MCHLT	R	0h	Sticky bit indicating that the modulator clock halt condition 0 = did not occurred since last read 1 = occurred since last read
5-2	Reserved	R	0h	Reserved
1	Reserved	R	0h	Reserved
0	Reserved	R	0h	Reserved

9.7.32 STATUS_POWER (book=0x00 page=0x00 address=0x2A) [reset=0h]

This register indicated the operational status of various internal blocks

Figure 87. STATUS_POWER Register Address: 0x2A

7	6	5	4	3	2	1	0
SPWR_DAC	SPWR_CD	SPWR_BST	SPWR_BSTPT	SPWR_ISNS	SPWR_VSNS	Reserved
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 90. Status Block Power Field Descriptions

Bit	Field	Type	Reset	Description
7	SPWR_DAC	R	0h	The DAC block is 0 = powered down 1 = powered up
6	SPWR_CD	R	0h	The Class-D block is 0 = powered down 1 = powered up
5	SPWR_BST	R	0h	The boost block is 0 = powered down 1 = powered up
4	SPWR_BSTPT	R	0h	The boost pass-thru is 0 = disabled 1 = enabled
3	SPWR_ISNS	R	0h	The i-sense block is 0 = powered down 1 = powered up
2	SPWR_VSNS	R	0h	The v-sense block is 0 = powered down 1 = powered up
1-0	Reserved	R	0h	Reserved

9.7.33 SAR_VBAT_MSB (book=0x00 page=0x00 address=0x2D) [reset=C0h]

SAR VBAT Measurement MSB

Figure 88. SAR_VBAT_MSB Register Address: 0x2D

7	6	5	4	3	2	1	0
SAR_VBAT[9:2]
R-C0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 91. SAR VBAT Measurement MSB Field Descriptions

Bit	Field	Type	Reset	Description
7--2	SAR_VBAT[9:0]	R	C0h	The VBAT measurement from the SAR ADC when enabled

9.7.34 SAR_VBAT_LSB (book=0x00 page=0x00 address=0x2E) [reset=0h]

SAR VBAT Measurement LSB

Figure 89. SAR_VBAT_LSB Register Address: 0x2E

7	6	5	4	3	2	1	0
SAR_VBAT[1:0]		Reserved
R-0h		R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 92. SAR VBAT Measurement LSB Field Descriptions

Bit	Field	Type	Reset	Description
7-6	SAR_VBAT[1:0]	R	0h	The VBAT measurement from the SAR ADC when enabled
5-0	Reserved	R	0h	Reserved

9.7.35 DIE_TEMP_SENSOR (book=0x00 page=0x00 address=0x31) [reset=0h]

Request a die temperature reading and register to read back the die temperature range.

Figure 90. DIE_TEMP_SENSOR Register Address: 0x31

7	6	5	4	3	2	1	0
Reserved		DTMP_INIT	DTMP_VALID	DTMP_VAL[3:0]
RW-0h		RW-0h	R-0h	R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 93. Die Temperature Sensor Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	RW	0h	Reserved
5	DTMP_INIT	RW	0h	Request a reading of the die temperature be performed. The die temp measurement acquisition is 0 = idle 1 = Initiated (self cleared when completed)
4	DTMP_VALID	R	0h	Indicated the validity of the die temperature registers. This will be invalid when the acquisition is in progress. Die temperature reading is 0 = invalid 1 = valid
3-0	DTMP_VAL[3:0]	R	0h	The last die temperature measurement was 0 = less than 30 C 1 = in the range 30 C to 50 C 2 = in the range 50 C to 65 C 3 = in the range 65 C to 80 C 4 = in the range 80 C to 85 C 5 = in the range 85 C to 90 C 6 = in the range 90 C to 95 C 7 = in the range 95 C to 100 C 8 = in the range 100 C to 105 C 9 = in the range 105 C to 110 C 10 = in the range 110 C to 115 C 11 = in the range 115 C to 120 C 12 = in the range 120 C to 125 C 13 = in the range 125 C to 130 C 14 = in the range 130 C to 140 C 15 = is greater than 140 C

9.7.36 LOW_PWR_MODE (book=0x00 page=0x00 address=0x35) [reset=0h]

Sets the VBAT POR status to save idle current consumption in shutdown.

Figure 91. LOW_PWR_MODE Register Address: 0x35

7	6	5	4	3	2	1	0
VBAT_POR	Reserved
RW-0h	RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 94. Low Power Configuration Field Descriptions

Bit	Field	Type	Reset	Description
7	VBAT_POR	RW	0h	Set the VBAT POR block state. When the VBAT POR is disabled the lowest shutdown current can be obtained. The VBAT should remain powered up when the POR is disabled. The VBAT POR is 0 = powered up 1 = powered down
6-0	Reserved	RW	0h	Reserved

9.7.37 PCM_RATE (book=0x00 page=0x00 address=0x36) [reset=32h]

Sets the PCM input sampling rate

Figure 92. PCM_RATE Register Address: 0x36

7	6	5	4	3	2	1	0
Reserved		Reserved		Reserved		PCM_RATE[1:0]
RW-0h		RW-3h		RW-0h		RW-2h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 95. PCM Sample Rate Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	RW	0h	Reserved
5-4	Reserved	RW	3h	Reserved
3-2	Reserved	RW	3h	Reserved
1-0	PCM_RATE[1:0]	RW	0h	Configure the ASI PCM rate used to 0 = 8 kHz 1 = 16 kHz 2 = 48 kHz 3 = 96 kHz

9.7.38 CLOCK_ERR_CFG_1 (book=0x00 page=0x00 address=0x4F) [reset=0h]

Sets if the device will try to auto

Figure 93. CLOCK_ERR_CFG_1 Register Address: 0x4F

7	6	5	4	3	2	1	0
Reserved				CLK_ERR2_AR	CLK_ERR1_AR	Reserved
RW-0h				RW-0h	RW-0h	RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 96. Clock Error Configuration 1 Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Reserved	RW	0h	Reserved
3	CLK_ERR2_AR	RW	0h	When an error occurs on clock error 2 block the device will 0 = perform a recovery when condition clears 1 = will shutdown and require user recovery
2	CLK_ERR1_AR	RW	0h	When an error occurs on clock error 1 block the device will 0 = perform a recovery when condition clears 1 = will shutdown and require user recovery
1-0	Reserved	RW	0h	Reserved

9.7.39 CLOCK_ERR_CFG_2 (book=0x00 page=0x00 address=0x50) [reset=11h]

Sets if the device will try to auto

Figure 94. CLOCK_ERR_CFG_2 Register Address: 0x50

7	6	5	4	3	2	1	0
CLK_ERR_MR[1:0]		CLK_ERR1_TO[2:0]			CLK_ERR2_TO[2:0]
RW-0h		RW-2h			RW-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 97. Clock Error Configuration 2 Field Descriptions

Bit	Field	Type	Reset	Description
7-6	CLK_ERR_MR[1:0]	RW	0h	On clock error detection the channel gain will ramp-down at the rate 0 = 15us per dB 1 = 30us per dB 3 = 60us per dB 4 = 120us per dB
5-3	CLK_ERR1_TO[2:0]	RW	2h	Playback path is muted if clock input doesn't come to clock error detection1 block for 0 = 10.6 us 1 = 21.3 us 2 = 42.6 us 3 = 85.3 us 4 = 0.34 ms 5 = 0.68 ms 6 = 1.36 ms 7 = 2.73 ms
2-0	CLK_ERR2_TO[2:0]	RW	1h	Playback path is muted if clock input doesn't come to clock error detection2 block for 0 = 10.6 us 1 = 21.3 us 2 = 42.6 us 3 = 85.3 us 4 = 0.34 ms 5 = 0.68 ms 6 = 1.36 ms 7 = 2.73 ms

9.7.40 PROTECTION_CFG_1 (book=0x00 page=0x00 address=0x58) [reset=3h]

D Proteciton Configuration 1

Figure 95. PROTECTION_CFG_1 Register Address: 0x58

7	6	5	4	3	2	1	0
Reserved	Reserved	Reserved	Reserved	Reserved	PROT_OT_AR	Reserved	Reserved
RW-0h	RW-0h	RW-0h	RW-0h	RW-0h	RW-0h	RW-1h	RW-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 98. Class Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	RW	0h	Reserved
6	Reserved	RW	0h	Reserved
5	Reserved	RW	0h	Reserved
4	Reserved	RW	0h	Reserved
3	Reserved	RW	0h	Reserved
2	PROT_OT_AR	RW	0h	Die over temperature auto retry is 0 = enabled 1 = disabled
1	Reserved	RW	0h	Reserved
0	Reserved	RW	0h	Reserved

9.7.41 CRC_CHECKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]

Hold the running CRC8 checksum of I2C transactions

Figure 96. CRC_CHECKSUM Register Address: 0x7E

7	6	5	4	3	2	1	0
CRC_VAL[7:0]
RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 99. Checksum Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CRC_VAL[7:0]	RW	0h	Current CRC value. Writing to this register will reset the checksum

9.7.42 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]

Book Selection

Figure 97. BOOK Register Address: 0x7F

7	6	5	4	3	2	1	0
BOOK[7:0]
RW-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 100. Book Selection Field Descriptions

Bit	Field	Type	Reset	Description
7-0	BOOK[7:0]	RW	0h	Set the device book 0 = Book 0 1 = Book 1 ... 255 = Book 255

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9 Detailed Description

9.1 Overview

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 General I2C Operation

Table 1. I2C Address Selection

9.3.2 Single-Byte and Multiple-Byte Transfers

9.3.3 Single-Byte Write

9.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write

9.3.5 Single-Byte Read

9.3.6 Multiple-Byte Read

9.3.7 PLL

Table 2. PLL Scaling Registers

Table 3. PLL Clock Input Source

Table 4. PLL Clock Input Source

9.3.8 Clock Distribution

Table 5. Clocking Block Rates

9.3.9 Clock Error Detection

Table 6. Clock Error 1 Source

Table 7. Clock Error 2 Source

Table 8. Clock Error 1 Enable

Table 9. Clock Error 2 Source

Table 10. Clock Error 1 Timeout

Table 11. Clock Error 2 Timeout

Table 12. Clock Error Soft-mute Ramp Rate

9.3.10 Class-D Edge Rate Control

Table 13. Class-D Edge Rate Control

9.3.11 IV Sense

Table 14. I-Sense Current Range

Table 15. I-Sense Power Down

Table 16. V-Sense Power Down

9.3.12 Boost Control

Table 17. Boost Mode

9.3.13 Thermal Fold-back

9.3.14 Battery Guard AGC

9.3.15 Configurable Boost Current Limit (ILIM)

Table 18. Current Limit Settings

9.3.16 Fault Protection

9.3.16.1 Speaker Over-Current

9.3.16.2 Analog Under-Voltage

9.3.16.3 Die Over-Temperature

Table 19. Die Over-Temperature Auto-Retry

9.3.16.4 Clocking Faults

9.3.16.5 Brownout

Table 20. Power Down Error

9.3.17 Spread Spectrum vs Synchronized

Table 21. Ramp Clock Mode

Table 22. Ramp Clock Frequency

Table 23. Ramp SSM Mode

9.3.18 IRQs and Flags

Table 24. Interrupt Registers

Table 25. IRQ Pin Drive

Table 26. IRQ Pin Mode

Table 27. IRQ GPO Value

Table 28. IRQ Indicator Mode

9.3.19 CRC checksum for I2C

9.3.20 PurePath™ Console 3 Software TAS2560 Application

9.4 Device Functional Modes

9.4.1 Audio Digital I/O Interface

Table 29. ASI PCM Mode

Table 30. ASI PCM Input Word Length

Table 31. ASI PCM Channel Mode

Table 32. ASI WCLK Mode

Table 33. ASI WCLK Edge

Table 34. ASI Dividers Clock Source

Table 35. ASI WCLK Divider Power

Table 36. ASI WCLK Divider Ratio

Table 37. ASI BCLK Mode

Table 38. ASI BCLK Edge

Table 39. ASI BCLK Divider Power

Table 40. ASI BCLK Divider Ratio

Table 41. ASI OFFSET1

Table 42. ASI Tri-state

Table 43. ASI Bus-keeper

9.4.1.1 I2S Mode

9.4.1.2 DSP Mode

9.3.1 General I²C Operation

Table 1. I²C Address Selection

9.3.19 CRC checksum for I²C

9.4.1.1 I²S Mode