Addr |
Register |
Description |
Section |
0x00 |
PAGE0 |
Device Page |
PAGE0 (page=0x00 address=0x00) [reset=0h] |
0x01 |
SW_RESET |
Software Reset |
SW_RESET (page=0x00 address=0x01) [reset=1h] |
0x02 |
PWR_CTL |
Power Control |
PWR_CTL (page=0x00 address=0x02) [reset=8Eh] |
0x03 |
PB_CFG1 |
Playback Configuration 1 |
PB_CFG1 (page=0x00 address=0x03) [reset=20h] |
0x04 |
MISC_CFG1 |
Misc Configuration 1 |
MISC_CFG1 (page=0x00 address=0x04) [reset=C6h] |
0x05 |
MISC_CFG2 |
Misc Configuration 2 |
MISC_CFG2 (page=0x00 address=0x05) [reset=22h] |
0x06 |
TDM_CFG0 |
TDM Configuration 0 |
TDM_CFG0 (page=0x00 address=0x06) [reset=9h] |
0x07 |
TDM_CFG1 |
TDM Configuration 1 |
TDM_CFG1 (page=0x00 address=0x07) [reset=2h] |
0x08 |
TDM_CFG2 |
TDM Configuration 2 |
TDM_CFG2 (page=0x00 address=0x08) [reset=Ah] |
0x09 |
TDM_CFG3 |
TDM Configuration 3 |
TDM_CFG3 (page=0x00 address=0x09) [reset=10h] |
0x0A |
TDM_CFG4 |
TDM Configuration 4 |
TDM_CFG4 (page=0x00 address=0x0A) [reset=13h] |
0x0B |
TDM_CFG5 |
TDM Configuration 5 |
TDM_CFG5 (page=0x00 address=0x0B) [reset=2h] |
0x0C |
TDM_CFG6 |
TDM Configuration 6 |
TDM_CFG6 (page=0x00 address=0x0C) [reset=0h] |
0x0D |
TDM_CFG7 |
TDM Configuration 7 |
TDM_CFG7 (page=0x00 address=0x0D) [reset=4h] |
0x0E |
TDM_CFG8 |
TDM Configuration 8 |
TDM_CFG8 (page=0x00 address=0x0E) [reset=5h] |
0x0F |
TDM_CFG9 |
TDM Configuration 9 |
TDM_CFG9 (page=0x00 address=0x0F) [reset=6h] |
0x10 |
TDM_CFG10 |
TDM Configuration 10 |
TDM_CFG10 (page=0x00 address=0x10) [reset=7h] |
0x11 |
TDM_DET |
TDM Clock detection monitor |
TDM_DET (page=0x00 address=0x11) [reset=7Fh] |
0x12 |
LIM_CFG_0 |
Limiter Configuration 0 |
LIM_CFG_0 (page=0x00 address=0x12) [reset=12h] |
0x13 |
LIM_CFG_1 |
Limiter Configuration 1 |
LIM_CFG_1 (page=0x00 address=0x13) [reset=76h] |
0x14 |
BOP_CFG_0 |
Brown Out Prevention 0 |
BOP_CFG_0 (page=0x00 address=0x14) [reset=1h] |
0x15 |
BOP_CFG_1 |
Brown Out Prevention 1 |
BOP_CFG_1 (page=0x00 address=0x15) [reset=2Eh] |
0x18 |
GAIN_ICLA_CFG0 |
Inter Chip Limiter Alignment 0 |
GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=Ch] |
0x19 |
ICLA_CFG1 |
Inter Chip Limiter Alignment 1 |
ICLA_CFG1 (page=0x00 address=0x19) [reset=0h] |
0x1A |
INT_MASK0 |
Interrupt Mask 0 |
INT_MASK0 (page=0x00 address=0x1A) [reset=FCh] |
0x1B |
INT_MASK1 |
Interrupt Mask 1 |
INT_MASK1 (page=0x00 address=0x1B) [reset=A6h] |
0x1E |
INT_MASK6 |
Interrupt Mask 6- Interrupt masks. |
INT_MASK6 (page=0x00 address=0x1E) [reset=80h] |
0x24 |
INT_LTCH0 |
Latched Interrupt Readback 0 |
INT_LTCH0 (page=0x00 address=0x24) [reset=0h] |
0x25 |
INT_LTCH1 |
Latched Interrupt Readback 1 |
INT_LTCH1 (page=0x00 address=0x25) [reset=0h] |
0x28 |
INT_LTCH6 |
Latched Interrupt Readback 6 |
INT_LTCH6 (page=0x00 address=0x28) [reset=0h] |
0x2A |
VBAT_MSB |
SAR ADC Conversion 0 |
VBAT_MSB (page=0x00 address=0x2A) [reset=0h] |
0x2B |
VBAT_LSB |
SAR ADC Conversion 1 |
VBAT_LSB (page=0x00 address=0x2B) [reset=0h] |
0x2C |
TEMP |
SAR ADC Conversion 2 |
TEMP (page=0x00 address=0x2C) [reset=0h] |
0x30 |
INT_CLK |
Interrupt and Clock Error |
INT_CLK (page=0x00 address=0x30) [reset=19h] |
0x31 |
DIN_PD |
Digital Input Pin Pull Down |
DIN_PD (page=0x00 address=0x31) [reset=40h] |
0x32 |
MISC_CFG3 |
Misc Configuration 3 |
MISC_CFG3 (page=0x00 address=0x32) [reset=80h] |
0x33 |
BOOST_CFG1 |
Boost Configure 1 |
BOOST_CFG1 (page=0x00 address=0x33) [reset=34h] |
0x34 |
BOOST_CFG2 |
Boost Configure 2 |
BOOST_CFG2 (page=0x00 address=0x34) [reset=40h] |
0x35 |
BOOST_CFG3 |
Boost Configure 3 |
BOOST_CFG3 (page=0x00 address=0x35) [reset=78h] |
0x3D |
MISC_CFG4 |
Misc Configuration 4 |
MISC_CFG4 (page=0x00 address=0x3D) [reset=8h] |
0x3F |
TG_CFG0 |
Tone Generator |
TG_CFG0 (page=0x00 address=0x3F) [reset=0h] |
0x40 |
BOOST_CFG4 |
Boost Configure 4 |
BOOST_CFG4 (page=0x00 address=0x40) [reset=79h] |
0x41 |
TDM_CFG11 |
TDM Configuration 11 |
TDM_CFG11 (page=0x00 address=0x41) [reset=48h] |
0x42 |
IO_DRV1 |
PAD drain strength control 1 |
IO_DRV1 (page=0x00 address=0x42) [reset=0h] |
0x43 |
IO_DRV2 |
PAD drain strength control 2 |
IO_DRV2 (page=0x00 address=0x43) [reset=0h] |
0x44 |
IO_DRV3 |
PAD drain strength control 3 |
IO_DRV3 (page=0x00 address=0x44) [reset=0h] |
0x48 |
MISC_CFG5 |
Boost and Class-D Settings |
MISC_CFG5 (page=0x00 address=0x48) [reset=A0h] |
0x7D |
REV_ID |
Revision and PG ID |
REV_ID (page=0x00 address=0x7D) [reset=0h] |
0x7E |
I2C_CKSUM |
I2C Checksum |
I2C_CKSUM (page=0x00 address=0x7E) [reset=0h] |
0x7F |
BOOK |
Device Book |
BOOK (page=0x00 address=0x7F) [reset=0h] |