JAJSFI3A May 2018 – November 2018 TAS3251
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | CDST6 | CDST5 | CDST4 | CDST3 | CDST2 | CDST1 | CDST0 |
R/W | R | R | R | R | R | R | R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | R/W | 0 | Reserved |
6 | CDST6 | R | Clock Detector Status – This bit indicates whether the MCLK clock is present or not.
0: MCLK is present
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5 | CDST5 | R | This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled.
0: PLL is locked
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4 | CDST4 | R | This bit indicates whether the both LRCLK and SCLK are missing (tied low) or not.
0: LRCLK and/or SCLK is present 1: LRCLK and SCLK are missing |
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3 | CDST3 | R | This bit indicates whether the combination of current sampling rate and MCLK ratio is valid for clock auto set.
0: The combination of FS/MCLK ratio is valid
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2 | CDST2 | R | This bit indicates whether the MCLK is valid or not. The MCLK ratio must be detectable to be valid. There is a limitation with this flag, that is, when the low period of LRCLK is less than or equal to five SCLKs, this flag will be asserted (MCLK invalid reported).
0: MCLK is valid
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1 | CDST1 | R | This bit indicates whether the SCLK is valid or not. The SCLK ratio must be stable and in the range of 32-256FS to be valid.
0: SCLK is valid
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0 | CDST0 | R | This bit indicated whether the audio sampling rate is valid or not. The sampling rate must be detectable to be valid. There is a limitation with this flag, that is when this flag is asserted and P0-R37 is set to ignore all asserted error flags such that the DAC recovers, this flag will be de-asserted (sampling rate invalid not reported anymore).
0: Sampling rate is valid
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