SLAS844A May   2012  – January 2016 TAS5624A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics - Audio Specification Stereo (BTL)
    7. 7.7 Electrical Characteristics - Audio Specification 4 Channels (SE)
    8. 7.8 Electrical Characteristics - Audio Specification Mono (PBTL)
    9. 7.9 Typical Characteristics
      1. 7.9.1 BTL Configuration
      2. 7.9.2 SE Configuration
      3. 7.9.3 PBTL Configuration
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  System Power-Up and Power-Down Sequence
        1. 9.3.1.1 Powering Up
        2. 9.3.1.2 Powering Down
      2. 9.3.2  Start-Up and Shutdown Ramp Sequence
      3. 9.3.3  Unused Output Channels
      4. 9.3.4  Device Protection System
      5. 9.3.5  Pin-to-Pin Short-Circuit Protection (PPSC)
      6. 9.3.6  Overtemperature Protection
      7. 9.3.7  Overtemperature Warning, OTW
      8. 9.3.8  Undervoltage Protection (UVP) and Power-On Reset (POR)
      9. 9.3.9  Error Reporting
      10. 9.3.10 Fault Handling
      11. 9.3.11 Device Reset
      12. 9.3.12 System Design Consideration
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Pin Connections
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical SE Configuration
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Typical PBTL Configuration
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
    2. 11.2 Boot Strap Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material Recommendation
      2. 12.1.2 PVDD Capacitor Recommendation
      3. 12.1.3 Decoupling Capacitor Recommendation
      4. 12.1.4 Circuit Component and Printed-Circuit-Board Recommendation
        1. 12.1.4.1 Circuit Component Requirements
        2. 12.1.4.2 Printed-Circuit-Board Requirements
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

These typical connection diagrams highlight the required external components and system level connections for proper operation of the device in several popular use cases. Each of these configurations can be realized using the evaluation modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the most common modes of operation. Any design variation can be supported by TI through schematic and layout reviews. Visit the E2E Forum at www.e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional information.

10.2 Typical Applications

10.2.1 Typical BTL Application

See Figure 16 for application schematic. In this application, differential PWM inputs are used with AD modulation from the PWM modulator (TAS5558). AD modulation scheme is defined as PWM(+) as opposite polarity from PWM(–).

TAS5624A TAS5624A_2xBTL_SLAS844.gif Figure 16. Typical Differential (2N) BTL Application With AD Modulation Filters

10.2.1.1 Design Requirements

Table 5 lists the design parameters of Figure 16.

Table 5. Design Requirements

PARAMETER VALUE
Digital regulator supply 12 V
Full-bridge power supply 12 V to 38 V
PWM modulator TAS5558
Output filters Inductor-capacitor lowpass filter
Speaker 2.5 Ω minimum

10.2.1.2 Detailed Design Procedure

Using Figure 16 as a guide, integrate the hardware into the system schematic.

Following the recommended component placement, schematic layout and routing given in Layout Example, integrate the device and its supporting components into the system PCB file.

  • The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the high-frequency signals which go to the serial audio port. TI recommends that these be constructed to ensure they are given precedent as design trade-offs are made.
  • For questions and support go to the E2E Forum at www.e2e.ti.com. If it is necessary to deviate from the recommended layout, please visit the E2E Forum to request a layout review.

10.2.1.2.1 Pin Connections

  • Pin 1 - GVDD_AB is the gate-drive voltage for half-bridges A and B. It needs a 3.3-Ω isolation resistor and a 0.1-µF decoupling capacitor.
  • Pin 2 - VDD is the supply for internal voltage regulators AVDD and DVDD. It needs a 10-µF bulk capacitor and a 0.1-µF decoupling capacitor.
  • Pin 3 - Roc adjust is the overcurrent programming resistor. Depending on the application, this resistor can be between 24 kΩ to 68 kΩ.
  • Pin 4 - RESET pin when asserted, it keeps outputs Hi-Z and no PWM switching. This pin can be controlled by a microprocessor.
  • Pins 5 and 6 - These are PWM(+) and PWM(–) pins with signals provided by a PWM modulator such as the TAS5558. These are PWM differential pairs.
  • Pin 7 - Start-up ramp capacitor must be 1 µF for SE configuration.
  • Pin 8 - Digital output supply pin is connected to 1-µF decoupling capacitor.
  • Pins 9-12 - Ground pins are connected to board ground.
  • Pin 13 - Analog output supply pin is connected to 1-µF decoupling capacitor.
  • Pins 14 and 15 - These are PWM(+) and PWM(–) pins with signals provided by a PWM modulator such as the TAS5558. These are PWM differential pair.
  • Pin 16 - Fault pin can be monitored by a microcontroller through GPIO pin. System can decide to assert reset or shutdown.
  • Pin 17 - Overtemperature warning pin can be monitored by a microcontroller through a GPIO pin. System can decide to turn on fan or lower output power.
  • Pin 18 - Output clip indicator can be monitored by a microcontroller through a GPIO pin. System can decide to lower the volume.
  • Pins 19-21 - Mode pins set the input and output configurations. For this configuration M1-M3 are grounded. These mode pins must be hardware configured, such as, not through GPIO pins from a microcontroller.
  • Pin 22 - GVDD_CD is the gate-drive voltage for half-bridges C and D. This pin needs a 3.3-Ω isolation resistor and a 0.1-µF decoupling capacitor.
  • Pins 23, 24, 43, 44 - Bootstrap pins for half-bridges A, B, C, and D. Connect 33 nF from this pin to corresponding output pins.
  • Pins 25, 26, 33, 34, 41, 42 - These ground pins must be used to ground decoupling capacitors from PVDD_X.
  • Pins 27, 28, 32, 35, 39, 40 - Output pins from half-bridges A, B, C, and D. Connect appropriate bootstrap capacitors and differential LC filter as shown in Figure 20.
  • Pins 29, 30, 31, 36, 37, 38 - Power supply pins to half-bridges A, B, C, and D. A and B form a full-bridge and C and D form another full-bridge. A 470-µF bulk capacitor is recommended for each full-bridge power pins. Two 0.22-µF decoupling capacitors are placed on each full-bridge power pins. See Figure 20 for details.

10.2.1.3 Application Curves

TAS5624A TAS5624A_G006.png Figure 17. System Power Loss vs Output Power
TAS5624A TAS5624A_G007.png Figure 18. Output Power vs Temperature

10.2.2 Typical SE Configuration

See Figure 19 for application schematic. In this application, four single-ended PWM inputs are used with AD modulation from the PWM modulator such as the TAS5558. AD modulation scheme is defined as PWM(+) is opposite polarity from PWM(–). The single-ended (SE) output configuration is often used to drive four independent channels in one TAS5622A device.

TAS5624A TAS5624A_4xSE_SLAS844.gif Figure 19. Typical (1N) SE Application

10.2.2.1 Design Requirements

Design Requirements lists the design parameters of Figure 19.

10.2.2.2 Detailed Design Procedure

Using Figure 16 as a guide, follow the design procedure in Detailed Design Procedure.

10.2.2.3 Application Curves

TAS5624A TAS5624A_G009.png
Figure 20. Total Harmonic Distortion + Noise
vs Output Power
TAS5624A TAS5624A_G010.png
Figure 21. Output Power vs Supply Voltage

10.2.3 Typical PBTL Configuration

TAS5624A TAS5624A_1xPBTL_SLAS844.gif Figure 22. Typical Differential (2N) PBTL Application With AD Modulation Filter

10.2.3.1 Design Requirements

Design Requirements lists the design parameters of Figure 19.

10.2.3.2 Detailed Design Procedure

Using Figure 16 as a guide, follow the design procedure in Detailed Design Procedure.

10.2.3.3 Application Curves

TAS5624A TAS5624A_G011.png
Figure 23. Total Harmonic Distortion + Noise
vs Output Power
TAS5624A TAS5624A_G012.png
A.
Figure 24. Output Power vs Supply Voltage