10.3.1 Power Supply

To facilitate system design, the TAS5727 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.

To provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x), and power-stage supply pins (PVDD_x). The gate-drive voltage (GVDD_OUT) is derived from the PVDD voltage. Place all decoupling capacitors as close to their associated pins as possible. Inductance between the power-supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_OUT) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 288 kHz to 384 kHz, TI recommends using 33-nF, X7R ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.

Pay special attention to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is decoupled with a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.

The TAS5727 is fully protected against erroneous power-stage turnon due to parasitic gate charging.

10.3.2 I²C Address Selection and Fault Output

10.3.3 Device Protection Systems

10.3.4 Clock, Auto Detection, and PLL

The TAS5727 is an I²S slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the Clock Control Register (0x00).

The TAS5727 checks to verify that SCLK is a specific value of 32 f_S, 48 f_S, or 64 f_S. The DAP only supports a
1 × f_S LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock rates as defined in the clock-control register.

The TAS5727 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect changes and errors. Once the system detects a clock change or error, it mutes the audio (through a single-step mute) and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the system autodetects the new rate and reverts to normal operation. During this process, the default volume is restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0x0E).

10.3.5 PWM Section

The TAS5727 DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP and outputs two BTL PWM audio output channels.

The PWM section has individual-channel DC-blocking filters that can be enabled and disabled. The filter cutoff frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can be enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.

For a detailed description of using audio processing features like DRC and EQ, see the User's Guide (SLOU299) and the TAS57xx GDE.

10.3.6 SSTIMER Functionality

The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is shut down, the drivers are placed in the high-impedance state and transition slowly down through a 3-kΩ resistor, similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin capacitance. Larger capacitors increase the start-up time, while capacitors smaller than 2.2 nF decrease the start-up time. The SSTIMER pin should be left floating for BD modulation.

10.3.7 Single-Filter PBTL Mode

The TAS5727 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected before the LC filter. To put the part in PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the turnoff of half-bridges A and B (and similarly C/D) if an overcurrent condition is detected in either half-bridge. There is a pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating.

PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should be written with a value of 0x0110 3245. Also, the PWM shutdown register (0x19) should be written with a value of 0x3A.

10.3.8 I²C Serial Control Interface

10.3.8.1 General I²C Operation

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 18. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5727 holds SDA low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals through a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.

Figure 18. Typical I²C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 18.

The 7-bit address for TAS5715 is 0101 010 (0x54) or 0101 011 (0x56) defined by A_SEL (external pulldown for 0x54 and pullup for 0x56).

10.3.8.3 Single-Byte Write

As shown in Figure 19, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C device address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5727 internal memory address being accessed. After receiving the address byte, the TAS5727 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5727 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Figure 19. Single-Byte Write Transfer

10.3.8.4 Multiple-Byte Write

A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are transmitted by the master device to the DAP as shown in Figure 20. After receiving each data byte, the TAS5727 responds with an acknowledge bit.

Figure 20. Multiple-Byte Write Transfer

10.3.8.5 Single-Byte Read

As shown in Figure 21, a single-byte data-read transfer begins with the master device transmitting a start condition, followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5727 address and the read/write bit, TAS5727 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5727 address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5727 again responds with an acknowledge bit. Next, the TAS5727 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.

Figure 21. Single-Byte Read Transfer

10.3.8.6 Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the TAS5727 to the master device as shown in Figure 22. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 22. Multiple-Byte Read Transfer

10.3.9 Audio Serial Interface

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5727 DAP accepts serial data in 16-, 20-, or 24-bit left-justified, right-justified, and I²S serial data formats.

10.3.10 Serial Interface Control and Timing

10.3.10.1 I²S Timing

I²S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × f_S is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused trailing data bit positions.

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 23. I²S 64-f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 24. I²S 48-f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 25. I²S 32-f_S Format

10.3.10.2 Left-Justified

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × f_S is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions.

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 26. Left-Justified 64-f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 27. Left-Justified 48-f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 28. Left-Justified 32-f_S Format

10.3.10.3 Right-Justified

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × f_S is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions.

Figure 29. Right-Justified 64-f_S Format

Figure 30. Right-Justified 48-f_S Format

Figure 31. Right-Justified 32-f_S Format

10.3.11 Dynamic Range Control (DRC)

The DRC scheme has two DRC blocks. There is one ganged DRC for the high-band left and right channels and one DRC for the low-band left and right channels.

The DRC input/output diagram is shown in Figure 32.

Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
 • Each DRC has adjustable threshold levels.
 • Programmable attack and decay time constants
 • Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
    and decay times can be set slow enough to avoid pumping.

Figure 32. Dynamic Range Control

T = 9.23 format, all other DRC coefficients are 3.23 format

Figure 33. DRC Structure

10.3.12 PWM Level Meter

The structure in Figure 34 shows the PWM level meter that can be used to study the power profile.

Figure 34. PWM Level Meter Structure

10.4.1 Stereo BTL Mode

The classic stereo mode of operation uses the TAS5727 device to amplify two independent signals, which represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented on differential output pairs shown as OUT_A and OUT_B for a channel and OUT_C and OUT_D for the other one. The routing of the audio data which is presented on the OUT_x outputs can be changed according to the PWM Output Mux Register (0x25). By default, the TAS5727 device is configured to output channel 1 to the OUT_A and OUT_B outputs, and channel 2 to the OUT_C and OUT_D outputs. Stereo Mode operation outputs are shown in Figure 35.

Figure 35. Stereo BTL Mode

10.4.2 Mono PBTL Mode

When this mode of operation is used, the two stereo outputs of the device are placed in parallel one with another to increase the power sourcing capabilities of the device. The TAS5727 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected before the LC filter. The merging of the two output channels in this device can be done before the inductor portion of the output filter. This is called Single-Filter PBTL, and this mono operation is shown in Figure 36. More information about this can be found in Single-Filter PBTL Mode.

Figure 36. Mono PBTL Mode

10.5.1 26-Bit 3.23 Number Format

All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23 numbers means that there are 3 bits to the left of the binary point and 23 bits to the right of the binary point (see Figure 37).

Figure 37. 3.23 Format

The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 37. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 38 applied to obtain the magnitude of the negative number.

Figure 38. Conversion Weighting Factors—3.23 Format to Floating Point

Gain coefficients, entered through the I²C bus, must be entered as 32-bit binary numbers. Figure 39 shows the format of the 32 bit number (4 byte or 8 digit hexadecimal number).

Figure 39. Alignment of 3.23 Coefficient in 32-Bit I²C Word

Table 4. Serial Control Interface Register Summary

10.6.1 Clock Control Register (0x00)

The clocks and data rates are automatically determined by the TAS5727. The clock control register contains the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.

10.6.2 Device Id Register (0x01)

The device ID register contains the ID code for the firmware revision.

10.6.3 Error Status Register (0x02)

The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors.

Error definitions:

• MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK error: The number of SCLKs per LRCLK is changing.
• LRCLK error: LRCLK frequency is changing.
• Frame slip: LRCLK phase is drifting with respect to internal frame sync.

10.6.4 System Control Register 1 (0x03)

System control register 1 has several functions:

10.6.5 Serial Data Interface Register (0x04)

As shown in Table 9, the TAS5727 supports nine serial data modes. The default is 24-bit, I²S mode.

10.6.6 System Control Register 2 (0x05)

When bit D6 is set low, the system exits all-channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute).

Ternary modulation is disabled by default. To enable ternary modulation, the following writes are required before bringing the system out of shutdown:

1. Set bit D3 of register 0x05 to 1.
2. Write the following ICD settings:
   1. 0x11= 80
   2. 0x12= 7C
   3. 0x13= 80
   4. 0x24 =7C
3. Set the input mux register as follows:
   1. 0x20 = 00 89 77 72

10.6.7 Soft Mute Register (0x06)

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).

10.6.8 Volume Registers (0x07, 0x08, 0x09)

Step size is 0.125 dB and volume registers are 2 bytes.

10.6.9 Volume Configuration Register (0x0E)

In two-band DRC, register 0x0A should be set to 0x30 and register 0x0E bits 6 and 5 should be set to 1.

10.6.10 Modulation Limit Register (0x10)

10.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)

Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

ICD settings have high impact on audio performance (for example, dynamic range, THD, crosstalk, and so forth) Therefore, appropriate ICD settings must be used. By default, the device has ICD settings for the AD mode. If used in BD mode, then update these registers before coming out of all-channel shutdown.

10.6.12 PWM Shutdown Group Register (0x19)

Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D5 in the system control register.

This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is set to 0 in system control register 2, 0x05).

10.6.13 Start/Stop Period Register (0x1A)

This register is used to control the soft-start and soft-stop period following an enter or exit all-channel shutdown command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times are only approximate and vary depending on device activity level and I²S clock stability.

10.6.14 Oscillator Trim Register (0x1B)

The TAS5727 PWM processor contains an internal oscillator to support autodetect of I²S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO.

Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.

Note that trim must always be run following reset of the device.

10.6.15 BKND_ERR Register (0x1C)

When a back-end error signal is received from the internal power stage, the power stage is reset, stopping all PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 20 before attempting to re-start the power stage.

10.6.16 Input Multiplexer Register (0x20)

This register controls the modulation scheme (AD or BD mode) as well as the routing of I²S audio to the internal channels.

10.6.17 Channel 4 Source Select Register (0x21)

This register selects the channel 4 source.