JAJSCJ5B September   2016  – October 2017 TAS6424-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     PCB領域
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Parameter measurement Information
  10. 10Detailed description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Serial Audio Port
        1. 10.3.1.1 I2S Mode
        2. 10.3.1.2 Left-Justified Timing
        3. 10.3.1.3 Right-Justified Timing
        4. 10.3.1.4 TDM Mode
        5. 10.3.1.5 Supported Clock Rates
        6. 10.3.1.6 Audio-Clock Error Handling
      2. 10.3.2  High-Pass Filter
      3. 10.3.3  Volume Control and Gain
      4. 10.3.4  High-Frequency Pulse-Width Modulator (PWM)
      5. 10.3.5  Gate Drive
      6. 10.3.6  Power FETs
      7. 10.3.7  Load Diagnostics
        1. 10.3.7.1 DC Load Diagnostics
        2. 10.3.7.2 Line Output Diagnostics
        3. 10.3.7.3 AC Load Diagnostics
      8. 10.3.8  Protection and Monitoring
        1. 10.3.8.1 Overcurrent Limit (ILIMIT)
        2. 10.3.8.2 Overcurrent Shutdown (ISD)
        3. 10.3.8.3 DC Detect
        4. 10.3.8.4 Clip Detect
        5. 10.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. 10.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 10.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)
        8. 10.3.8.8 Overvoltage (OV) and Load Dump
      9. 10.3.9  Power Supply
        1. 10.3.9.1 Vehicle-Battery Power-Supply Sequence
        2. 10.3.9.2 Boosted Power-Supply Sequence
      10. 10.3.10 Hardware Control Pins
        1. 10.3.10.1 FAULT
        2. 10.3.10.2 WARN
        3. 10.3.10.3 MUTE
        4. 10.3.10.4 STANDBY
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operating Modes and Faults
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Communication Bus
      2. 10.5.2 I2C Bus Protocol
      3. 10.5.3 Random Write
      4. 10.5.4 Sequential Write
      5. 10.5.5 Random Read
      6. 10.5.6 Sequential Read
    6. 10.6 Register Maps
      1. 10.6.1  Mode Control Register (address = 0x00) [default = 0x00]
        1. Table 10. Mode Control Field Descriptions
      2. 10.6.2  Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
        1. Table 11. Misc Control 1 Field Descriptions
      3. 10.6.3  Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
        1. Table 12. Misc Control 2 Field Descriptions
      4. 10.6.4  SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
        1. Table 13. SAP Control Field Descriptions
      5. 10.6.5  Channel State Control Register (address = 0x04) [default = 0x55]
        1. Table 14. Channel State Control Field Descriptions
      6. 10.6.6  Channel 1 Through 4 Volume Control Registers (address = 0x05–0x088) [default = 0xCF]
        1. Table 15. Ch x Volume Control Field Descriptions
      7. 10.6.7  DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
        1. Table 16. DC Load Diagnostics Control 1 Field Descriptions
      8. 10.6.8  DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
        1. Table 17. DC Load Diagnostics Control 2 Field Descriptions
      9. 10.6.9  DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
        1. Table 18. DC Load Diagnostics Control 3 Field Descriptions
      10. 10.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
        1. Table 19. DC Load Diagnostics Report 1 Field Descriptions
      11. 10.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
        1. Table 20. DC Load Diagnostics Report 2 Field Descriptions
      12. 10.6.12 DC Load Diagnostics Report 3—Line Output—Register (address = 0x0E) [default = 0x00]
        1. Table 21. DC Load Diagnostics Report 3—Line Output—Field Descriptions
      13. 10.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
        1. Table 22. State-Reporting Field Descriptions
      14. 10.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
        1. Table 23. Channel Faults Field Descriptions
      15. 10.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
        1. Table 24. Global Faults 1 Field Descriptions
      16. 10.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
        1. Table 25. Global Faults 2 Field Descriptions
      17. 10.6.17 Warnings Register (address = 0x13) [default = 0x20]
        1. Table 26. Warnings Field Descriptions
      18. 10.6.18 Pin Control Register (address = 0x14) [default = 0xFF]
        1. Table 27. Pin Control Field Descriptions
      19. 10.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
        1. Table 28. AC Load Diagnostic Control 1 Field Descriptions
      20. 10.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
        1. Table 29. AC Load Diagnostic Control 2 Field Descriptions
      21. 10.6.21 AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17–0x1A) [default = 0x00]
        1. Table 30. Chx AC LDG Impedance Report Field Descriptions
      22. 10.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
        1. Table 31. AC LDG Phase High Report Field Descriptions
      23. 10.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
        1. Table 32. AC LDG Phase Low Report Field Descriptions
      24. 10.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
        1. Table 33. AC LDG STI High Report Field Descriptions
      25. 10.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1C) [default = 0x00]
        1. Table 34. Chx AC LDG STI Low Report Field Descriptions
      26. 10.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
        1. Table 35. Misc Control 3 Field Descriptions
      27. 10.6.27 Clip Control Register (address = 0x22) [default = 0x01]
        1. Table 36. Clip Control Field Descriptions
      28. 10.6.28 Clip Window Register (address = 0x23) [default = 0x14]
        1. Table 37. Clip Window Field Descriptions
      29. 10.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
        1. Table 38. Clip Warning Field Descriptions
      30. 10.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
        1. Table 39. ILIMIT Status Field Descriptions
      31. 10.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
        1. Table 40. Misc Control 4 Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 AM-Radio Band Avoidance
      2. 11.1.2 Parallel BTL Operation (PBTL)
      3. 11.1.3 Demodulation Filter Design
      4. 11.1.4 Line Driver Applications
    2. 11.2 Typical Applications
      1. 11.2.1 BTL Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Power Supplies
        3. 11.2.1.3 Communication
        4. 11.2.1.4 Detailed Design Procedure
          1. 11.2.1.4.1 Hardware Design
          2. 11.2.1.4.2 Digital Input and the Serial Audio Port
          3. 11.2.1.4.3 Bootstrap Capacitors
          4. 11.2.1.4.4 Output Reconstruction Filter
        5. 11.2.1.5 Application Curves
      2. 11.2.2 PBTL Application
        1. 11.2.2.1 Design Requirements
          1. 11.2.2.1.1 Detailed Design Procedure
        2. 11.2.2.2 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Electrical Connection of Thermal pad and Heat Sink
      2. 13.1.2 EMI Considerations
      3. 13.1.3 General Guidelines
    2. 13.2 Layout Example
    3. 13.3 Thermal Considerations
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
      1. 14.1.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DKQ|56
サーマルパッド・メカニカル・データ
発注情報

8.7 Typical Characteristics

TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.11 MHz, AES17 filter, default I2C settings, see Figure 79 and Figure 82 (unless otherwise noted)
TAS6424-Q1 D002_SLOS870.gif
PO = 1 W
Figure 1. Crosstalk vs Frequency
TAS6424-Q1 D024_SLOS870.gif
PO = 1 W
Figure 3. VBAT PSRR vs Frequency
TAS6424-Q1 D006_SLOS870.gif
PO = 1 W 2.11-MHz fSW
Figure 5. THD+N vs Frequency
TAS6424-Q1 D008_SLOS870.gif
PO = 1 W 24 V 2.11-MHz fSW
Figure 7. THD+N vs Frequency
TAS6424-Q1 D010_SLOS870.gif
2.11-MHz fSW
Figure 9. THD+N vs Power
TAS6424-Q1 D012_SLOS870.gif
24 V 2.11-MHz fSW
Figure 11. THD+N vs Power
TAS6424-Q1 D014_SLOS870.gif
10% THD 2.11-MHz fSW
Figure 13. Output Power vs Supply Voltage
TAS6424-Q1 D016_SLOS870.gif
A-weighted Noise 2.11-MHz fSW
Figure 15. Noise vs Supply voltage
TAS6424-Q1 D020_SLOS870.gif
4 Ω 2.1-MHz fSW
Figure 17. Power Efficiency vs Output Power
TAS6424-Q1 D018_SLOS870.gif
2 Ω 2.1-MHz fSW
Figure 19. Power Efficiency vs Output Power
TAS6424-Q1 D026_SLOS870.gif
Figure 21. VBAT Current vs Voltage
TAS6424-Q1 D028_SLOS870.gif
1 W 384-kHz fSW
Figure 23. PBTL THD+N vs Frequency
TAS6424-Q1 D030_SLOS870.gif
PO = 1 W 384-kHz fSW 24-V PVDD
Figure 25. PBTL THD+N vs Frequency
TAS6424-Q1 D032_SLOS870.gif
384-kHz fSW
Figure 27. PBTL THD+N vs Power
TAS6424-Q1 D034_SLOS870.gif
384-kHz fSW
Figure 29. PBTL THD+N vs Power
TAS6424-Q1 D036_SLOS870.gif
384-kHz fSW
Figure 31. Output Power vs Voltage
TAS6424-Q1 D038_SLOS870.gif
384-kHz fSW
Figure 33. Power Dissipation vs Output Power
TAS6424-Q1 D022_SLOS870.gif
PO = 1 W
Figure 2. PVDD PSRR vs Frequency
TAS6424-Q1 D005_SLOS870.gif
PO = 1 W 384-kHz fSW
Figure 4. THD+N vs Frequency
TAS6424-Q1 D007_SLOS870.gif
PO = 1 W 24 V 384-kHz fSW
Figure 6. THD+N vs Frequency
TAS6424-Q1 D009_SLOS870.gif
384-kHz fSW
Figure 8. THD+N vs Power
TAS6424-Q1 D011_SLOS870.gif
24 V 384-kHz fSW
Figure 10. THD+N vs Power
TAS6424-Q1 D013_SLOS870.gif
10% THD 384-kHz fSW
Figure 12. Output Power vs Supply Voltage
TAS6424-Q1 D015_SLOS870.gif
A-weighted Noise 384-kHz fSW
Figure 14. Noise vs Supply Voltage
TAS6424-Q1 D019_SLOS870.gif
4 Ω 384-kHz fSW
Figure 16. Power Efficiency vs Output Power
TAS6424-Q1 D017_SLOS870.gif
2 Ω 384-kHz fSW
Figure 18. Power Efficiency vs Output Power
TAS6424-Q1 D025_SLOS870.gif
Figure 20. PVDD Current vs Voltage
TAS6424-Q1 D027_SLOS870.gif
Figure 22. PVDD Standby Current vs Voltage
TAS6424-Q1 D029_SLOS870.gif
PO = 1 W 2.1-MHz fSW
Figure 24. PBTL THD+N vs Frequency
TAS6424-Q1 D031_SLOS870.gif
Po = 1 W 2.1-MHz fSW 24-V PVDD
Figure 26. PBTL THD+N vs Frequency
TAS6424-Q1 D033_SLOS870.gif
2.1-MHz fSW
Figure 28. PBTL THD+N vs Power
TAS6424-Q1 D035_SLOS870.gif
2.1-MHz fSW 24-V PVDD
Figure 30. PBTL THD+N vs Power
TAS6424-Q1 D037_SLOS870.gif
2.1-MH fSW
Figure 32. Output Power vs Voltage
TAS6424-Q1 D039_SLOS870.gif
2.1-MHz fSW
Figure 34. Power Dissipation vs Output Power