JAJSGL7C December   2012  – December 2018 TCA9517A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 I2C Interface Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Two-Channel Bidirectional Buffer
      2. 9.3.2 Active-High Repeater-Enable Input
      3. 9.3.3 VOL B-Side Offset Voltage
      4. 9.3.4 Standard Mode and Fast Mode Support
      5. 9.3.5 Clock Stretching Support
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Clock Stretching Support
        2. 10.2.2.2 VILC and Pullup Resistor Sizing
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VCCB = 2.7 V to 5.5 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS VCCB MIN TYP MAX UNIT
VIK Input clamp voltage II = –18 mA 2.7 V to 5.5 V –1.2 V
VOL Low-level output voltage SDAB, SCLB IOL = 100 μA or 6 mA,
VILA = VILB = 0 V		 2.7 V to 5.5 V 0.45 0.52 0.6 V
SDAA, SCLA IOL = 6 mA 0.1 0.2
VOL – VILc Low-level input voltage below low-level output voltage SDAB, SCLB ensured by design 2.7 V to 5.5 V 70 mV
VILC SDA and SCL low-level input voltage contention SDAB, SCLB 2.7 V to 5.5 V 0.45 V
ICC Quiescent supply current for VCCA Both channels low,
SDAA = SCLA = GND and
SDAB = SCLB = open, or
SDAA = SCLA = open and
SDAB = SCLB = GND		 1 mA
ICC Quiescent supply current Both channels high,
SDAA = SCLA = VCCA and
SDAB = SCLB = VCCB and
EN = VCCB 		5.5 V 1.5 5 mA
Both channels low,
SDAA = SCLA = GND and
SDAB = SCLB = open		 1.5 5
In contention,
SDAA = SCLA = GND and
SDAB = SCLB = GND		 3 5
II Input leakage current SDAB, SCLB VI = VCCB 2.7 V to 5.5 V ±1 μA
VI = 0.2 V 10
SDAA, SCLA VI = VCCB ±1
VI = 0.2 V 10
EN VI = VCCB ±1
VI = 0.2 V –10 –30
IOH High-level output leakage current SDAB, SCLB VO = 3.6 V 2.7 V to 5.5 V 10 μA
SDAA, SCLA 10
CI Input capacitance EN VI = 3 V or 0 V 3.3 V 6 10 pF
SCLA, SCLB VI = 3 V or 0 V 3.3 V 8 13
0 V 7 11
CIO Input/output capacitance SDAA, SDAB VI = 3 V or 0 V 3.3 V 8 13 pF
0 V 7 11