JAJSSB8 November   2023 TDP2004

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP 2.1 Mainlink Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5.2.2 Channel Registers

Table 6-9 EQ Gain Control Register (Channel register base + Offset = 0x01)
BitFieldTypeResetDescription
7eq_stage1_bypassR/W0x0

Enable EQ stage 1 bypass:

0: Bypass disabled

1: Bypass enabled

6eq_stage1_3R/W0x0

EQBoost stage 1 control

See Table 6-1 for details

5eq_stage1_2R/W0x0
4eq_stage1_1R/W0x0
3eq_stage1_0R/W0x0
2eq_stage2_2R/W0x0

EQ Boost stage 2 control

See Table 6-1 for details

1eq_stage2_1R/W0x0
0eq_stage2_0R/W0x0
Table 6-10 EQ Gain / Flat Gain Control Register (Channel register base + Offset = 0x03)
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6eq_profile_3R/W0x0

EQ mid-frequency boost profile

See Table 6-1 for details

5eq_profile_2R/W0x0
4eq_profile_1R/W0x0
3eq_profile_0R/W0x0
2flat_gain_2R/W0x1

Flat gain select:

See Table 6-2 for details

1flat_gain_1R/W0x0
0flat_gain_0R/W0x1
Table 6-11 TI Test Mode Control Register (Channel register base + Offset = 0x04)
BitFieldTypeResetDescription
7-3, 1-0RESERVEDR0x0Reserved
2TI test modeR/W0x0

Set TI test mode:

0: test mode is enabled

1: test mode is disabled. Must be set to "1" for normal operation.

Table 6-12 PD Override Register (Channel register base + Offset = 0x05)
BitFieldTypeResetDescription
7device_en_overrideR/W0x0Enable power down overrides through SMBus/I2C

0: Manual override disabled

1: Manual override enabled

6-0device_enR/W0x111111Manual power down of redriver various blocks of a channel – gated by device_en_override = 1

111111: All blocks in the channel are enabled

000000: All blocks in the channel are disabled

Table 6-13 Bias Register (Channel register base + Offset = 0x06)
BitFieldTypeResetDescription
5-3Bias currentR/W0x100Control bias current

Set 001 for best performance

7,6,2-0ReservedR/W0x00000Reserved