JAJSSB8A November   2023  – April 2024 TDP2004

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP 2.1 Mainlink Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RNQ|40
サーマルパッド・メカニカル・データ
発注情報

Shared Registers

Table 6-6 General Registers (Offset = 0xE2)
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6rst_i2c_regsR/W/SC0x0Device reset control: Reset all I2C registers to default values (self-clearing).
5rst_i2c_masR/W/SC0x0Reset I2C Primary (self-clearing).
4-1RESERVEDR0x0Reserved
0frc_eeprm_rdR/W/SC0x0Override MODE and READ_EN_N status to force manual EEPROM configuration load.
Table 6-7 EEPROM_Status Register (Offset = 0xE3)
BitFieldTypeResetDescription
7eecfg_cmpltR0x0EEPROM load complete.
6eecfg_failR0x0EEPROM load failed.
5eecfg_atmpt_1R0x0Number of attempts made to load EEPROM image.
4eecfg_atmpt_0R0x0
3eecfg_cmpltR0x0EEPROM load complete 2.
2eecfg_failR0x0EEPROM load failed 2.
1eecfg_atmpt_1R0x0Number of attempts made to load EEPROM image 2.
0eecfg_atmpt_0R0x0
Table 6-8 DEVICE_ID0 Register (Offset = 0xF0)
BitFieldTypeResetDescription
7-4RESERVEDR0x0Reserved
3device_id0_3R0x0Device ID0 [3:1]: 011
2device_id0_2R0x1
1device_id0_1R0x1
0RESERVEDRXReserved
Table 6-9 DEVICE_ID1 Register (Offset = 0xF1)
BitFieldTypeResetDescription
7device_id[7]R0x0Device ID 0010 1001: TDP2004
6device_id[6]R0x0
5device_id[5]R0x1
4device_id[4]R0x0
3device_id[3]R0x1
2device_id[2]R0x0
1device_id[1]R0x0
0device_id[0]R0x0