JAJSDF9D July   2017  – June 2019 TIOL111 , TIOL1113 , TIOL1115

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  Wake Up Detection
      2. 9.3.2  Current Limit Configuration
      3. 9.3.3  Current Fault Detection, Indication and Auto Recovery
      4. 9.3.4  Thermal Warning, Thermal Shutdown
      5. 9.3.5  Fault Reporting (NFAULT)
      6. 9.3.6  Transceiver Function Tables
      7. 9.3.7  The Integrated Voltage Regulator (LDO)
      8. 9.3.8  Reverse Polarity Protection
      9. 9.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 9.3.10 Power Up Sequence (TIOL111)
      11. 9.3.11 Undervoltage Lock-Out (UVLO)
    4. 9.4 Device Functional Modes
      1. 9.4.1 NPN Configuration (N-Switch SIO Mode)
      2. 9.4.2 PNP Configuration (P-Switch SIO Mode)
      3. 9.4.3 Push-Pull, Communication Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Maximum Junction Temperature Check
        2. 10.2.2.2 Driving Capacitive Loads
        3. 10.2.2.3 Driving Inductive Loads
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.9 Integrated Surge Protection and Transient Waveform Tolerance

The L+ and CQ pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC 61000-4-5 surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100 nF supply decoupling capacitor between L+ and L-, and 1 µF between VCC_IN/OUT and L-.

External TVS diodes may be required for higher transient protection levels. The system designer should ensure that the maximum clamping voltage of the external diodes should be < 65 V at the desired current level. The device is capable of withstanding up to ±65-V transient pulses < 100 µs.

TIOL111 TIOL1113 TIOL1115 surge_test_setup_sllsev5.gif
1.2/50 – 8/20 µs CWG
R = 500 Ω
Figure 16. Surge Test Setup