SGLS416 January   2015 TLC2274-HT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, VDD = 5 V
    6. 6.6 Operating Characteristics, VDD = 5 V
    7. 6.7 Electrical Characteristics, VDD± = ±5 V
    8. 6.8 Operating Characteristics, VDD± = ±5 V
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Macromodel Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Macromodel Information

Macromodel information provided was derived using Microsim Parts, the model generation software used with Microsim PSpice. The Boyle macromodel

G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974).
and subcircuit in Figure 46 are generated using the TLC227x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):

  • Maximum positive output voltage swing
  • Maximum negative output voltage swing
  • Slew rate
  • Quiescent power dissipation
  • Input bias current
  • Open-loop voltage amplification
  • Unity-gain frequency
  • Common-mode rejection ratio
  • Phase margin
  • DC output resistance
  • AC output resistance
  • Short-circuit output current limit
subcir_gls404.gifFigure 46. Boyle Macromodels and Subcircuit

8.2 Typical Application

The TLC2274 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 48 and Figure 49 show its ability to drive loads up to 1000 pF while maintaining good gain and phase margins (Rnull = 0).

sch_series_resistance_GLS416.gifFigure 47. Typical Application Schematic

8.2.1 Design Requirements

As per Equation 1:

Table 2. Design Parameters

Improvement in Phase Margin UGBW (kHz) R null (Ω) CL (pF)
0 1000 0 1000
7.15 1000 20 1000
17.43 1000 50 1000
32.12 1000 100 1000

8.2.2 Detailed Design Procedure

A smaller series resistor (Rnull) at the output of the device (see Figure 47) improves the gain and phase margins when driving large capacitive loads. Figure 48 and Figure 49 show the effects of adding series resistances of 10 Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two effects: the first is that it adds a zero to the transfer function and the second is that it reduces the frequency of the pole associated with the output load in the transfer function.

The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To calculate the improvement in phase margin, Equation 1 can be used.

Equation 1. Δφm1 = tan–1 (2 × π × UGBW × Rnull × CL)

where

  • Δφm1 = Improvement in phase margin
  • UGBW = Unity-gain bandwidth frequency
  • Rnull = Output series resistance
  • CL = Load capacitance

The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 47). To use equation 1, UGBW must be approximated from Figure 47. Using Equation 1 alone overestimates the improvement in phase margin, as illustrated in Figure 51. The overestimation is caused by the decrease in the frequency of the pole associated with the load, thus providing additional phase shift and reducing the overall improvement in phase margin. Using Figure 47, with Equation 1 enables the designer to choose the appropriate output series resistance to optimize the design of circuits driving large capacitance loads.

8.2.3 Application Curves

TA = 25°C
phase_CL_gls404.gif
Figure 48. Phase Margin vs Load Capacitance
app_unity-gain_GLS416.gif
Figure 50. Unity-Gain Bandwidth vs Load Capacitance
gain_CL_gls404.gif
Figure 49. Gain Margin vs Load Capacitance
app_overest_GLS416.gif
Figure 51. Overestimation of Phase Margin vs Load Capacitance