JAJSO93A データシート

JAJSO93A May 2022 – December 2022 TLIN1431-Q1

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

RGY|20

サーマルパッド・メカニカル・データ

発注情報

jajso93a_oa

6.7 Electrical Characteristics

parameters valid over –40℃ ≤ T_J ≤ 150 ℃ range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
RXD Output Terminal
V_OH	High level output voltage	I_O = –2 mA, V_CC = Active	0.8			V_CC
V_OL	Low level output voltage	I_O = 2 mA, V_CC = Active			0.2	V_CC
I_LKG(OFF)	Unpowered leakage current	Outputs = 5.25/3.465 V, V_CC = V_SUP = 0 V	–1		1	µA
TXD Input Terminal
V_IL	Low level input voltage		–0.3		0.8	V
V_IH	High level input voltage		2		5.5	V
I_IH	High level input leakage current	TXD = V_IH	–5	0	5	µA
R_TXD	Internal pull-up resistor value		125	350	800	kΩ
LIN Terminal (Referenced to V_SUP)
V_OH	HIGH level output voltage⁽⁵⁾	LIN recessive, TXD = high, I_O = 0 mA, V_SUP = 5.5 V to 28 V	0.85			V_SUP
V_OL	LOW level output voltage⁽⁵⁾	LIN dominant, TXD = low, V_SUP = 5.5 V to 28 V			0.2	V_SUP
V_{SUP_NON_OP}	V_SUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11)	TXD & RXD open V_LIN = 5.5 V to 45 V	–0.3		45	V
I _{BUS_LIM}	Limiting current (ISO/DIS 17987 Param 12)	TXD = 0 V, V_LIN = 28 V, R_MEAS = 440 Ω, V_SUP = 28 V, V_BUSdom ≤ 0.251 * V_SUP	40	90	200	mA
I _{BUS_PAS_dom}	Receiver leakage current, dominant (ISO/DIS 17987 Param 13)	V_LIN = 0 V, V_SUP = 12 V Driver off/recessive	–1			mA
I _{BUS_PAS_rec1}	Receiver leakage current, recessive (ISO/DIS 17987 Param 14)	V_LIN ≥ V_SUP, 5.5 V ≤ V_SUP ≤ 28 V Driver off			20	µA
I _{BUS_PAS_rec2}	Receiver leakage current, recessive (ISO/DIS 17987 Param 14)	V_LIN = V_SUP, Driver off	–5		5	µA
I _{BUS_NO_GND}	Leakage current, loss of ground (ISO/DIS 17987 Param 15)	GND = V_SUP, V_SUP = 12 V, 0 V ≤ V_LIN ≤ 28 V	–1		1	mA
I_{BUS_NO_BAT}	Leakage current, loss of supply (ISO/DIS 17987 Param 16)	0 V ≤ V_LIN ≤ 28 V, V_SUP = GND			10	µA
V_BUSdom	Low level input voltage (ISO/DIS 17987 Param 17)	LIN dominant (including LIN dominant for wake up); Figure 7-2			0.4	V_SUP
V_BUSrec	High level input voltage (ISO/DIS 17987 Param 18)	LIN recessive; Figure 7-2	0.6			V_SUP
V_{BUS_CNT}	Receiver center threshold (ISO/DIS 17987 Param 19)	V_{BUS_CNT} = (V_IL + V_IH)/2; Figure 7-2	0.475	0.5	0.525	V_SUP
V_HYS	Hysteresis voltage (ISO/DIS 17987 Param 20)⁽⁶⁾⁽⁷⁾	V_HYS = (V_IL - V_IH); Figure 7-2			0.175	V_SUP
V_{SERIAL_DIODE}	Serial diode LIN term pull-up path (ISO/DIS 17987 Param 21)	By design and characterization	0.4	0.7	1.0	V
R_LIN	Internal pull-up resistor to V_SUP on LIN (ISO/DIS 17987 Param 26)	Normal and Standby modes	20	45	60	kΩ
I_RSLEEP	Pull-up current source to V_SUP	Sleep mode, V_SUP = 12 V, LIN = GND	–20		–2	µA
C_LIN,PIN	Capacitance of the LIN pin	By design and characterization			25	pF
EN Input Terminal
V_IH	High level input voltage		2		5.5	V
V_IL	Low level input voltage				0.8	V
V_HYS	Hysteresis voltage	By design and characterization	30		500	mV
I_IL	Low level input current	EN = Low	–8		8	µA
R_EN	Internal pull-down resistor		125	350	800	kΩ
LIMP Output Terminal (High Voltage Open-drain Output)
ΔV_H	Hi-level voltage drop for LIMP with respect to V_SUP	I_LIMP = –60 mA		0.42	1.2	V
R_dson	LIMP output drain-to-source on resistance	I_O = –60 mA		7	20	Ω
I_LKG(LIMP)	Leakage current	LIMP = 0 V, Sleep Mode	–1		1	µA
HSS, INH high voltage open drain output pin
V_{DET_INH}	Voltage on INH/WKRQ pin during t_{DET_INH}time	VSUP = 14V			1.5	V
ΔV_HINH	Hi-level voltage drop for INH with respect to V_SUP	I_INH = –6 mA		0.5	1	V
ΔV_HHSS	Hi-level voltage drop for HSS with respect to V_SUP	I_HSS = –60 mA		0.42	1.2	V
R_dson	HSS output drain-to-source on resistance	I_O = –60 mA		7	17	Ω
I_O(HSS)	Output current support	VSUP = 14 V,		60	100	mA
I_OC(HSS)	HSS overcurrent limit	VSUP = 14 V	150		300	mA
I_OL(HSS)	HSS open load current	VSUP = 14 V	–2.5			mA
I_OLHYS(HSS)	HSS open load current hysteresis	VSUP = 14 V	0.05	0.45	1	mA
I_lkg	Leakage current	INH, HSS = 0 V, Sleep Mode	–1		1	µA
t_R/F	Output rise and fall times (HSS)	5.5 V ≤ V_SUP ≤ 28 V, I_LOAD = 60 mA, R_L = 220 Ω, 80%/20%	0.6		2.5	V/µs
t_{HSS_on}	Switching on delay (HSS) from SPI command to on	V_SUP = 14 V, I_LOAD = 60 mA, V_OUT = 80% of V_SUP			60	µs
t_{HSS_off}	Switching off delay (HSS) from SPI command to off	V_SUP = 14 V, I_LOAD = 60 mA, V_OUT = 20% of V_SUP			140	µs
t_OCFLTR	HSS overcurrent filter time(2)	V_SUP = 14 V		16		µs
t_OLFLTR	HSS open load filter time(2)	V_SUP = 14 V		64		µs
t_OCOFF	HSS overcurrent shut off time	I_O(HSS) > I_OC(HSS)	200		300	µs
WAKE Input Terminal
V_IH	High-level input voltage	Sleep or Standby Mode, WAKE pin enabled	4			V
V_IL	Low-level input voltage	Sleep or Standby Mode, WAKE pin enabled			2	V
I_IL	Low-level input leakage current	WAKE = 1 V		15	25	µA
t_WAKE	Wake up hold time from a wake edge on WAKE in standby or sleep mode for static sensing..	See Figure 8-44 and Figure 8-45	140			µs
t_{WAKE_INVALID}	WAKE pin pulses shorter than this will be filtered out in standby or sleep mode for static and cyclic sensing.	See Figure 8-44 and Figure 8-45			10	µs
WDI, SDI, CLK, nCS Input Terminal
V_IH	High-level input voltage		2.19			V
V_IL	Low-level input voltage				0.8	V
I_IH	High-level input leakage current	Inputs = V_CC	–1		1	µA
I_IL	Low-level input leakage current	Inputs = 0 V, V_CC = Active	–50			µA
C_IN	Input Capacitance	4 MHz		10	15	pF
I_LKG(OFF)	Unpowered leakage current	Inputs = 5.25/3.465 V, V_CC = V_SUP = 0 V	–1		1	µA
R_{WDI_SDIpu}	Internal pull-up resistor on WDI/SDI pin		100	240	400	kΩ
R_CLKpu	Internal pull-up resistor on WDT/CLK pin	SPI control only for CLK	100	240	400	kΩ
R_nCSpu	Internal pull-up resistor on PIN/nCS pin	SPI control only for nCS	100	240	400	kΩ
WDT Input Terminal
V_IH	High-level input voltage	Inputs = V_CC	0.8			V_CC
V_IL	Low-level input voltage	Inputs = V_CC			0.2	V_CC
V_IM(WDT)	WDT Mid-level input voltage⁽¹⁾	Inputs = V_CC	0.4	0.5	0.6	V_CC
I_IH	High-level input leakage current	Inputs = V_CC	2.5		25	µA
I_IL	Low-level input leakage current	Inputs = 0 V, V_CC = Active	–25		–2.5	µA
I_LKG(OFF)	Unpowered leakage current	Inputs = 5.25/3.465 V, V_CC = V_SUP = 0 V	–3		3	µA
SDO Output Terminal
V_OH	High level output voltage	I_O = –2 mA, V_CC = Active	0.8			V_CC
V_OL	Low level output voltage	I_O = 2 mA, V_CC = Active			0.2	V_CC
I_LKG(OFF)	Unpowered leakage current	Outputs = 5.25/3.465 V, V_CC = V_SUP = 0 V	–1		1	µA
nRST Terminal; input/output reset (Open-drain)
I_LKG	Leakage current, high-level	LIN = V_SUP, nRST = V_CC	–5		5	µA
V_OL	Low-level output voltage	Based upon external pull up to V_CC			0.2	V_CC
I_OL	Low-level output current, open drain	LIN = 0 V, nRST = 0.4 V	1.5			mA
V_th(sw)	Switching threshold voltage		0.25		0.75	V_CC
R_PU	Pull-up resistance		30	45	65	kΩ
nINT, nWDR, WKRQ Terminal
V_OH	High level output voltage	I_O = –2 mA, V_CC = Active	0.8			V_CC
V_OL	Low-level output voltage	I_O = 2 mA, V_CC = Active			0.2	V_CC
I_LKG(OFF)	Unpowered leakage current (nINT and nWDR pins)	Outputs = 5.25/3.465 V, V_CC = V_SUP = 0 V	–1		1	µA
HSSC
V_IH	High-level input voltage		2		5.5	V
V_IL	Low-level input voltage				0.8	V
I_IL	Low-level input current	V_IN = 0 V	–1		1	µA
R_HSSC	Pull-down resistor		150	350	800	kΩ
f_SW	Switching frequency	V_HSS = 14 V, I_O(HSS) = 60 mA			400	Hz
WDI, WDT TIMING and SWITCHING CHARACTERISTIC (RL = 1 MΩ, CL = 50 pF and T_J = -40°C to 150°C)
t_W	WDI pulse width; see Figure 7-8	Filter time to avoid false input	30			µs
t_WINDOW	Closed Window + Open Window; See Figure 7-8	WDT = GND	32	40	48	ms
		WDT = V_CC	480	600	720	ms
		WDT = Floating	4.8	6	7.2	s
DIV_ON
V_IH	High-level input voltage		2		5.5	V
V_IL	Low-level input voltage				0.8	V
I_IL	Low-level input current	V_{DIV_ON} = 0 V	–1		1	µA
R_{DIV_ON}	Pull-down resistor		150	370	800	kΩ
PV
Ratio	Divider ratio 5 V VCC	V_BAT = 5.5 V to 28 V		1:7
Ratio	Divider ratio 3.3 V VCC	V_BAT = 5.5 V to 20 V		1:9
ERR	Divider ratio error	V_BAT = 5.5 V to 28 V	–2		2	%
V_BATLIN5	Linear voltage range for V_BAT for 5 V LDO⁽³⁾	R_LOAD = 470 Ω ± 5% and C_LOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20%, 5.5 V ≤ V_BAT ≤ 28 V	0.735		4.05	V
V_BATLIN3	Linear voltage range for V_BAT for 3.3 V LDO and when I/O is 3.3 V with 5 V LDO⁽⁴⁾	R_LOAD = 470 Ω ± 5% and C_LOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20%, 5.5 V ≤ V_BAT ≤ 20 V	0.561		2.27	V
V_MAX5V	Maximum V_PVOUT	28 V < V_BAT ≤ 42 V, 470 Ω ± 5% and C_LOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20%			5.1	V
V_MAX3.3V	Maximum V_PVOUTfor 3.3 V LDO and when I/O is 3.3 V with 5 V LDO	20 V < V_BAT ≤ 42 V, 470 Ω ± 5% and C_LOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20%			3.36	V
V_{VCC5V_VIO3V}	Voltage when VCC = 5 V and I/O is at 3.3 V	R_LOAD = 470 Ω ± 5% and C_LOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20% and I/O voltage is ≤ 3.6 V			3.36	V
C_PIN	Pin capacitance			12		pF
t_SET	Settling time of the buffer	470 Ω ± 5% and C_LOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20%			50	µs
Duty Cycle Characteristics
D1	Duty Cycle 1 (ISO/DIS 17987 Param 27 and J2602 Normal battery)⁽⁸⁾⁽⁹⁾	TH_REC(MAX) = 0.744 x V_SUP, TH_DOM(MAX) = 0.581 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 50/52 µs, D1 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure 7-3, Figure 7-4)	0.396
D2	Duty Cycle 2 (ISO/DIS 17987 Param 28 and J2602 Normal battery)⁽⁸⁾⁽⁹⁾	TH_REC(MIN) = 0.422 x V_SUP, TH_DOM(MIN) = 0.284 x V_SUP, V_SUP = 7.6 V to 18 V, t_BIT = 50/52 µs, D2 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 7-3, Figure 7-4)			0.581
D3	Duty Cycle 3 (ISO/DIS 17987 Param 29 and J2602 Normal battery)⁽⁸⁾⁽⁹⁾	TH_REC(MAX) = 0.778 x V_SUP, TH_DOM(MAX) = 0.616 x V_SUP, V_SUP= 7.0 V to 18 V, t_BIT = 96 µs, D3 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure 7-3, Figure 7-4)	0.417
D4	Duty Cycle 4 (ISO/DIS 17987 Param 30 and J2602 Normal battery)⁽⁸⁾⁽⁹⁾	TH_REC(MIN) = 0.389 x V_SUP, TH_DOM(MIN) = 0.251 x V_SUP, V_SUP= 7.6 V to 18 V, t_BIT = 96 µs, D4 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 7-3, Figure 7-4)			0.59
D1_LB	Duty Cycle 1 J2602 Low battery⁽⁹⁾⁽¹⁰⁾	TH_REC(MAX) = 0.665 x V_SUP, TH_DOM(MAX) = 0.499 x V_SUP, V_SUP = 5.5 V to 7 V, t_BIT = 50/52 µs, D1 = t_{BUS_rec(min)/(2 x tBIT)} (See Figure 7-3, Figure 7-4)	0.396
D2_LB	Duty Cycle 2 J2602 Lowl battery⁽⁹⁾⁽¹⁰⁾	TH_REC(MIN) = 0.496 x V_SUP, TH_DOM(MIN) = 0.361 x V_SUP, V_SUP = 6.1 V to 7.6 V, t_BIT = 50/52 µs, D2 = t_{BUS_rec(MAX})/(2 x t_BIT) (See Figure 7-3, Figure 7-4)			0.581
D3_LB	Duty Cycle 3 J2602 Low battery⁽⁹⁾⁽¹⁰⁾	TH_REC(MAX) = 0.665 x V_SUP, TH_DOM(MAX) = 0.499 x V_SUP, V_SUP = 5.5 V to 7 V, t_BIT = 96 µs, D1 = t_{BUS_rec(min)/(2 x tBIT)} (See Figure 7-3, Figure 7-4)	0.417
D4_LB	Duty Cycle 4 J2602 Lowl battery⁽⁹⁾⁽¹⁰⁾	TH_REC(MIN) = 0.496 x V_SUP, TH_DOM(MIN) = 0.361 x V_SUP, V_SUP = 6.1 V to 7.6 V, t_BIT = 96 µs, D2 = t_{BUS_rec(MAX})/(2 x t_BIT) (See Figure 7-3, Figure 7-4)			0.59

(1) This is the measured voltage at the WDT pin when left floating. The WDT pin should be connected directly to V_CC, GND or left floating.

(2) Specified by design

(3) V_BATLIN5 = [(1/7) * V_BAT] +/- 50 mV for the linear range of the PV buffer

(4) V_BATLIN3 = [(1/9) * V_BAT] +/- 50 mV for the linear range of the PV buffer

(5) SAE J2602 loads include: commander node: 5.5 nF; 4 kΩ and for a responder node: 5.5 nF; 875 Ω

(6) V_HYS is defined for both ISO 17987 and SAE J2602-1.

(7) V_HYS = (V_{th_rec} - V_{th_dom}) where V_{th_rec} and V_{th_dom} are the actual voltage values from V_BUSrec and V_BUSdom

(8) ISO 17987 loads include 1 nF; 1 kΩ/ 6.8nF; 660 Ω/ 10 nF; 500 Ω; with t_BIT values of 50 µs and 96 µs

(9) SAE J2602 loads include: commander node: 5.5 nF; 4 kΩ/ 899 pF; 20 kΩ and for a responder node: 5.5 nF; 875 Ω/ 899 pF; 900 Ω; with t_BIT values of 52 µs and 96 µs

(10) ISO 17987 does not have a low battery specification. Using the ISO 17987 loads these low battery duty cycle parameters are covered for t_BIT values of 50 µs and 96 µs