JAJSL93B March   2021  – February 2024 TLIN2029A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings - IEC
    4. 5.4 Thermal Information
    5. 5.5 Recommended Operating Conditions
    6. 5.6 Electrical Characteristics
    7. 5.7 Duty Cycle Characteristics
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  LIN (Local Interconnect Network) Bus
        1. 7.3.1.1 LIN Transmitter Characteristics
        2. 7.3.1.2 LIN Receiver Characteristics
          1. 7.3.1.2.1 Termination
      2. 7.3.2  TXD (Transmit Input and Output)
      3. 7.3.3  RXD (Receive Output)
      4. 7.3.4  VSUP (Supply Voltage)
      5. 7.3.5  GND (Ground)
      6. 7.3.6  EN (Enable Input)
      7. 7.3.7  Protection Features
      8. 7.3.8  TXD Dominant Time Out (DTO)
      9. 7.3.9  Bus Stuck Dominant System Fault: False Wake Up Lockout
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Under Voltage on VSUP
      12. 7.3.12 Unpowered Device and LIN Bus
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Wake Up Events
        1. 7.4.4.1 Wake Up Request (RXD)
        2. 7.4.4.2 Mode Transitions
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Normal Mode Application Note
        2. 8.2.2.2 Standby Mode Application Note
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Electrical Characteristics

parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply
VSUP Operational supply voltage (ISO/DIS 17987 Param 10) Device is operational beyond the LIN defined nominal supply voltage range See Figure 8-1 and Figure 8-2 4 48 V
VSUP Nominal supply voltage (ISO/DIS 17987 Param 10) Normal and Standby Modes: ramp VSUP while LIN signal is a 10 kHz square wave with 50 % duty cycle and 36V swing. See Figure 8-1 and Figure 8-2 4   48 V
Sleep Mode 4   48 V
UVSUP Under voltage VSUP threshold Min is falling edge and Max is rising edge 2.9 3.85 V
UVHYS Delta hysteresis voltage for VSUP under voltage threshold 0.2 V
ISUP Supply current Normal Mode: EN = high, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF  1.2 5 mA
Standby Mode: EN = low, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF  1 2.1 mA
ISUP Supply current Normal Mode: EN = high, bus recessive: LIN = VSUP,   400 700 µA
Standby Mode: EN = low, bus recessive: LIN = VSUP,   20 35 µA
Sleep Mode: 4.0 V < VSUP ≤ 27 V, LIN = VSUP, EN = 0 V, TXD and RXD floating   9 15 µA
Sleep Mode: 27 V < VSUP ≤ 48 V, LIN = VSUP, EN = 0 V, TXD and RXD floating     30 µA
TSD Thermal shutdown 165 ℃
TSD(HYS) Thermal shutdown hysteresis 15 ℃
RXD Output Pin (Open Drain)
VOL Output low voltage Based upon external pull-up to VCC (4) 0.6 V
IOL Low level output current, open drain LIN = 0 V, RXD = 0.4 V 1.5 mA
IILG Leakage current, high-level LIN = VSUP, RXD = 5 V –5 0 5 µA
TXD Input Pin
VIL Low level input voltage –0.3 0.8 V
VIH High level input voltage 2 5.25 V
IILG Low level input leakage current TXD = low –5 0 5 µA
RTXD Internal pull-down resistor value 125 350 800 kΩ
LIN PIN
VOH HIGH level output voltage (3) LIN recessive, TXD = high, IO = 0 mA, 7 V ≤ VSUP ≤ 48 V 0.85 VSUP
VOH LIN recessive high-level output voltage (1) (2) TXD = high, IO = 0 mA, 7 V ≤ VSUP ≤ 18 V 0.8 VSUP
VOH HIGH level output voltage(3) LIN recessive, TXD = high, IO = 0 mA, VSUP = 4 V ≤ VSUP < 7 V 3 V
VOL LOW level output voltage(3) LIN dominant, TXD = low, VSUP = 7 V to 48 V 0.2 VSUP
VOL LIN dominant low-level output voltage (1) (2) TXD = low, 7 V ≤ VSUP ≤ 18 V 0.2 VSUP
VOL LOW level output voltage(3) LIN dominant, TXD = low, VSUP = 4 V ≤ VSUP < 7 V 1.2 V
VSUP_NON_OP VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11) TXD & RXD open LIN = 4 V to 58 V –0.3 58 V
IBUS_LIM Limiting current (ISO/DIS 17987 Param 57) TXD = 0 V, VLIN = 36 V, RMEAS = 440 Ω, VSUP = 36 V, VBUSdom < 4.518 V 75 120 300 mA
IBUS_PAS_dom Receiver leakage current, dominant (ISO/DIS 17987 Param 13, 58) LIN = 0 V, VSUP = 24 V Driver off/recessive, Figure 8-6 –1 mA
IBUS_PAS_rec1 Receiver leakage current, recessive (ISO/DIS 17987 Param 14, 59) LIN > VSUP, 4 V ≤ VSUP ≤ 45 V Driver off; Figure 8-7 20 µA
IBUS_PAS_rec2 Receiver leakage current, recessive (ISO/DIS 17987 Param 14, 59) LIN = VSUP, Driver off; Figure 8-7 –5 5 µA
IBUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Param 15, 60) GND = VSUP, VSUP = 27 V, LIN = 0 V; Figure 8-8 –1 1 mA
IBUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Param 15, 60) GND = VSUP, VSUP ≥ 36 V, LIN = 0 V; Figure 8-8 –1.5 1.5 mA
Ileak gnd(dom) Leakage current, loss of ground (5) VSUP = 8 V, GND = open, VSUP = 18 V,
GND = open
RCommander = 1 kΩ, CL = 1 nF
RResponder = 20 kΩ, CL = 1 nF
LIN = dominant		 -1 1 mA
Ileak gnd(rec) Leakage current, loss of ground (5) VSUP = 8 V, GND = open, VSUP = 18 V,
GND = open
RCommander = 1 kΩ, CL = 1 nF
RResponder = 20 kΩ, CL = 1 nF
LIN = recessive		 -100 100 µA
IBUS_NO_BAT Leakage current, loss of supply (ISO/DIS 17987 Param 16, 61) LIN = 48 V, VSUP = GND; Figure 8-9 5 µA
VBUSdom Low level input voltage (ISO/DIS 17987 Param 17, 62) LIN dominant (including LIN dominant for wake up) See Figure 8-4, Figure 8-3 0.4 VSUP
VBUSrec High level input voltage (ISO/DIS 17987 Param 18, 63) LIN recessive See Figure 8-4, Figure 8-3 0.6 VSUP
VIH LIN recessive high-level input voltage (1) (2) 7 V ≤ VSUP ≤ 18 V 0.47 0.6 VSUP
VIL LIN dominant low-level input voltage (1) (2) 7 V ≤ VSUP ≤ 18 V 0.4 0.53 VSUP
VBUS_CNT Receiver center threshold (ISO/DIS 17987 Param 19, 64) VBUS_CNT = (VBUSrec + VBUSdom)/2 See Figure 8-4, Figure 8-3 0.475 0.5 0.525 VSUP
VHYS Hysteresis voltage (ISO/DIS 17987 Param 20, 65) VHYS = (VBUSrec - VBUSdom) See Figure 8-4, Figure 8-3 0.175 VSUP
VHYS Hysteresis voltage (SAE J2602) VHYS = VIH - VIL See Figure 8-4, Figure 8-3 0.07 0.175 VSUP
VSERIAL_DIODE Serial diode LIN termination pull-up path  ISERIAL_DIODE = 10 μA 0.4 0.7 1 V
RPU Internal pull-up resistor to VSUP Normal and standby modes 20 45 60 kΩ
IRSLEEP Pull-up current source to VSUP Sleep mode, VSUP = 27 V, LIN = GND –20 –2 µA
CLINPIN Capacitance of the LIN pin VSUP = 14 V 25 pF
EN Input Pin
VIL Low level input voltage –0.3 0.8 V
VIH High level input voltage 2 5.25 V
VIT Hysteresis voltage By design and characterization 50 500 mV
IILG Low level input current EN = low –5 0 5 µA
REN Internal pull-down resistor 125 350 800 kΩ
(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ
(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω
(3) ISO 17987 bus load conditions (CLINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.
(4) RXD uses open drain output structure therefore VOL level is based upon microcontroller supply voltage VCC.
(5) Ileak gnd = (VBAT - VLIN)/RLoad