JAJSCG3 September   2016 TLV171 , TLV2171 , TLV4171

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: TLV171
    5. 6.5 Thermal Information: TLV2171
    6. 6.6 Thermal Information: TLV4171
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Characteristics
      2. 7.3.2 Phase-Reversal Protection
      3. 7.3.3 Electrical Overstress
      4. 7.3.4 Capacitive Load and Stability
    4. 7.4 Device Functional Modes
      1. 7.4.1 Common-Mode Voltage Range
      2. 7.4.2 Overload Recovery
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 TINA-TI™ (無料のダウンロード・ソフトウェア)
        2. 11.1.1.2 DIPアダプタ評価モジュール
        3. 11.1.1.3 ユニバーサル・オペアンプ評価モジュール
        4. 11.1.1.4 TI Precision Designs
        5. 11.1.1.5 WEBENCHFilter Designer
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

TLV171: DBV Package
5-Pin SOT-23
Top View
TLV171 TLV2171 TLV4171 po_sot23-5_bos557.gif
TLV171: D Package
8-Pin SOIC
Top View
TLV171 TLV2171 TLV4171 po_so-8_bos557.gif

Pin Functions: TLV171

PIN I/O DESCRIPTION
NAME TLV171
DBV D
IN– 4 2 I Negative (inverting) input
IN+ 3 3 I Positive (noninverting) input
NC(1) — 1, 5, 8 — No internal connection (can be left floating)
OUT 1 6 O Output
V+ 5 7 — Positive (highest) power supply
V– 2 4 — Negative (lowest) power supply
(1) NC indicates no internal connection.
TLV2171: D and DGK Packages
8-Pin SOIC and VSSOP
Top View
TLV171 TLV2171 TLV4171 po_vssop-8_bos557.gif

Pin Functions: TLV2171

PIN I/O DESCRIPTION
NAME TLV2171
D DGK
–IN A 2 2 I Inverting input, channel A
–IN B 6 6 I Inverting input, channel B
+IN A 3 3 I Noninverting input, channel A
+IN B 5 5 I Noninverting input, channel B
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
V– 4 4 — Negative (lowest) power supply
V+ 8 8 — Positive (highest) power supply
TLV4171: D and PW Packages
14-Pin SOIC and TSSOP
Top View
TLV171 TLV2171 TLV4171 po_so-14_bos557.gif

Pin Functions: TLV4171

PIN I/O DESCRIPTION
NAME D PW
–IN A 2 2 I Inverting input, channel A
+IN A 3 3 I Noninverting input, channel A
–IN B 6 6 I Inverting input, channel B
+IN B 5 5 I Noninverting input, channel B
–IN C 9 9 I Inverting input, channel C
+IN C 10 10 I Noninverting input, channel C
–IN D 13 13 I Inverting input, channel D
+IN D 12 12 I Noninverting input, channel D
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
OUT C 8 8 O Output, channel C
OUT D 14 14 O Output, channel D
V– 11 11 — Negative (lowest) power supply
V+ 4 4 — Positive (highest) power supply