JAJSLB5C December   2021  – December 2023 TLV3801 , TLV3802 , TLV3811

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs
      2. 7.4.2 LVDS Output
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Capacitive Loads
      2. 8.1.2 Hysteresis
    2. 8.2 Typical Application
      1. 8.2.1 Optical Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Non-Inverting Comparator With Hysteresis
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
      3. 8.2.3 Logic Clock Source to LVDS Transceiver
      4. 8.2.4 External Trigger Function for Oscilloscopes
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.2 Detailed Design Procedure

First, create an equation for VT that covers both output voltages when the output is high or low.
Equation 5. GUID-00DC46C2-EC7D-440F-B116-67DF64784D3D-low.svg
Equation 6. GUID-FD4947BD-6101-4EC3-92C1-473377336555-low.svg
The hysteresis voltage in this network is equal to the difference in the two threshold voltage equations.
Equation 7. GUID-23EAC9D1-8372-4DCA-B7E3-876527A65EF1-low.svg
Equation 8. GUID-274800EF-823E-4308-A8CC-B7AF00ED7086-low.svg
Equation 9. GUID-E1A0B579-6624-41C4-9D8B-42E9E9ED4A3D-low.svg
Equation 10. GUID-B427E761-D89F-4E51-9DB1-24369CF204C9-low.svg
Note that these equations do not take into account the effects of the internal hysteresis and offset voltage of the comparator. Design parameters will need to be adjusted accordingly. Select a value for R2. Plug in given values for VREF, VT1, VT2, Q, and Q, and solve for R1. For the given example, R2 = 50 kΩ, and R1 is solved as = 8.3 kΩ.