JAJSP27A September   2022  – September 2023 TMAG5173-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Temperature Sensor
    7. 6.7  Magnetic Characteristics For A1, B1, C1, D1
    8. 6.8  Magnetic Characteristics For A2, B2, C2, D2
    9. 6.9  Magnetic Temp Compensation Characteristics
    10. 6.10 I2C Interface Timing
    11. 6.11 Power up Timing
    12. 6.12 Timing Diagram
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Magnetic Flux Direction
      2. 7.3.2 Sensor Location
      3. 7.3.3 Interrupt Function
      4. 7.3.4 Device I2C Address
      5. 7.3.5 Magnetic Range Selection
      6. 7.3.6 Update Rate Settings
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby (Trigger) Mode
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Continuous Measure Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 SCL
        2. 7.5.1.2 SDA
        3. 7.5.1.3 I2C Read/Write
          1. 7.5.1.3.1 Standard I2C Write
          2. 7.5.1.3.2 General Call Write
          3. 7.5.1.3.3 Standard 3-Byte I2C Read
          4. 7.5.1.3.4 1-Byte I2C Read Command for 16-Bit Data
          5. 7.5.1.3.5 1-Byte I2C Read Command for 8-Bit Data
          6. 7.5.1.3.6 I2C Read CRC
      2. 7.5.2 Data Definition
        1. 7.5.2.1 Magnetic Sensor Data
        2. 7.5.2.2 Temperature Sensor Data
        3. 7.5.2.3 Angle and Magnitude Data Definition
        4. 7.5.2.4 Magnetic Sensor Offset Correction
    6. 7.6 TMAG5173-Q1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Select the Sensitivity Option
      2. 8.1.2 Temperature Compensation for Magnets
      3. 8.1.3 Sensor Conversion
        1. 8.1.3.1 Continuous Conversion
        2. 8.1.3.2 Trigger Conversion
        3. 8.1.3.3 Pseudo-Simultaneous Sampling
      4. 8.1.4 Magnetic Limit Check
      5. 8.1.5 Magnetic Threshold Band Cross Detection
      6. 8.1.6 Error Calculation During Linear Measurement
      7. 8.1.7 Error Calculation During Angular Measurement
    2. 8.2 Typical Applications
      1. 8.2.1 Angle Measurement
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Gain Adjustment for Angle Measurement
        3. 8.2.1.3 Application Curves
      2. 8.2.2 I2C Address Expansion
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 デバイスおよびドキュメントのサポート
    1. 9.1 ドキュメントのサポート
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 商標
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 TMAG5173-Q1 Registers

Table 7-6 lists the memory-mapped registers for the TMAG5173-Q1 registers. All register offset addresses not listed in Table 7-6 should be considered as reserved locations and the register contents should not be modified.

Table 7-6 TMAG5173-Q1 Registers
Offset Acronym Register Name Section
0h DEVICE_CONFIG_1 Configure Device Operation Modes Section 7.6.1
1h DEVICE_CONFIG_2 Configure Device Operation Modes Section 7.6.2
2h SENSOR_CONFIG_1 Sensor Device Operation Modes Section 7.6.3
3h SENSOR_CONFIG_2 Sensor Device Operation Modes Section 7.6.4
4h X_THR_CONFIG X Threshold Configuration Section 7.6.5
5h Y_THR_CONFIG Y Threshold Configuration Section 7.6.6
6h Z_THR_CONFIG Z Threshold Configuration Section 7.6.7
7h T_CONFIG Temp Sensor Configuration Section 7.6.8
8h INT_CONFIG_1 Configure Device Operation Modes Section 7.6.9
9h MAG_GAIN_CONFIG Configure Device Operation Modes Section 7.6.10
Ah MAG_OFFSET_CONFIG_1 Configure Device Operation Modes Section 7.6.11
Bh MAG_OFFSET_CONFIG_2 Configure Device Operation Modes Section 7.6.12
Ch I2C_ADDRESS I2C Address Register Section 7.6.13
Dh DEVICE_ID ID for the device die Section 7.6.14
Eh MANUFACTURER_ID_LSB Manufacturer ID lower byte Section 7.6.15
Fh MANUFACTURER_ID_MSB Manufacturer ID upper byte Section 7.6.16
10h T_MSB_RESULT Conversion Result Register Section 7.6.17
11h T_LSB_RESULT Conversion Result Register Section 7.6.18
12h X_MSB_RESULT Conversion Result Register Section 7.6.19
13h X_LSB_RESULT Conversion Result Register Section 7.6.20
14h Y_MSB_RESULT Conversion Result Register Section 7.6.21
15h Y_LSB_RESULT Conversion Result Register Section 7.6.22
16h Z_MSB_RESULT Conversion Result Register Section 7.6.23
17h Z_LSB_RESULT Conversion Result Register Section 7.6.24
18h CONV_STATUS Conversion Satus Register Section 7.6.25
19h ANGLE_RESULT_MSB Conversion Result Register Section 7.6.26
1Ah ANGLE_RESULT_LSB Conversion Result Register Section 7.6.27
1Bh MAGNITUDE_RESULT Conversion Result Register Section 7.6.28
1Ch DEVICE_STATUS Device_Diag Status Register Section 7.6.29

Complex bit access types are encoded to fit into small table cells. Table 7-7 shows the codes that are used for access types in this section.

Table 7-7 TMAG5173-Q1 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1CP W
1C
P		 Write
1 to clear
Requires privileged access
Reset or Default Value
-n Value after reset or the default value

7.6.1 DEVICE_CONFIG_1 Register (Offset = 0h) [Reset = 00h]

DEVICE_CONFIG_1 is shown in Table 7-8.

Return to the Summary Table.

Table 7-8 DEVICE_CONFIG_1 Register Field Descriptions
Bit Field Type Reset Description
7 CRC_EN R/W 0h Enables I2C CRC byte to be sent.
0h = CRC disabled
1h = CRC enabled
6-5 MAG_TEMPCO R/W 0h Temperature coefficient of the magnet.
0h = 0 %/°C (No temperature compensation)
1h = 0.12 %/°C (NdBFe)
2h = 0.03 %/°C (SmCo)
3h = 0.20 %/°C (Ceramic)
4-2 CONV_AVG R/W 0h Enables additional sampling of the sensor data to reduce the noise effect (or to increase resolution).
0h = 1x average, 10.0-kSPS (3-axes) or 20-kSPS (1 axis)
1h = 2x average, 5.7-kSPS (3-axes) or 13.3-kSPS (1 axis)
2h = 4x average, 3.1-kSPS (3-axes) or 8.0-kSPS (1 axis)
3h = 8x average, 1.6-kSPS (3-axes) or 4.4-kSPS (1 axis)
4h = 16x average, 0.8-kSPS (3-axes) or 2.4-kSPS (1 axis)
5h = 32x average, 0.4-kSPS (3-axes) or 1.2-kSPS (1 axis)
1-0 I2C_RD R/W 0h Defines the I2C read mode.
0h = Standard I2C 3-byte read command
1h = 1-byte I2C read command for 16bit sensor data and conversion status
2h = 1-byte I2C read command for 8 bit sensor MSB data and conversion status
3h = Reserved

7.6.2 DEVICE_CONFIG_2 Register (Offset = 1h) [Reset = 00h]

DEVICE_CONFIG_2 is shown in Table 7-9.

Return to the Summary Table.

Table 7-9 DEVICE_CONFIG_2 Register Field Descriptions
Bit Field Type Reset Description
7-5 THR_HYST R/W 0h Select threshold band for the interrupt function, or hysteresis for the switch function. As an example, with 40-mT range the threshold band or hysteresis value, when THR_HYST set at 2h, ((40/(211))*8 = 0.156 mT.
0h = Takes the 2's complement value of each x_THR_CONFIG register to create a magnetic threshold of the corresponding axis
1h = Takes the 7 LSB bits of the x_THR_CONFIG register to create two opposite magnetic thresholds (one north, and another south) of equal magnitude.
2h = 8 LSB threshold band, 12 bit resolution
3h = 16 LSB threshold band, 12 bit resolution
4h = 32 LSB threshold, band 12 bit resolution
5h = 64 LSB threshold band, 12 bit resolution
6h = 128 LSB threshold band, 12 bit resolution
7h = 256 LSB threshold band, 12 bit resolution
4 LP_LN R/W 0h Selects the modes between low active current or low-noise modes.
0h = Low active current mode
1h = Low noise mode
3 I2C_GLITCH_FILTER R/W 0h I2C glitch filter.
0h = Glitch filter on
1h = Glitch filter off
2 TRIGGER_MODE R/W 0h Selects a condition which initiates a single conversion based off already configured registers. A running conversion completes before executing a trigger. Redundant triggers are ignored. TRIGGER_MODE is available only during the mode explicitly mentioned in OPERATING_MODE.
0h = Conversion starts at I2C command bits, default
1h = Conversion starts through a trigger signal at the INT pin
1-0 OPERATING_MODE R/W 0h Selects the device operating mode.
0h = Standby mode (starts new conversion at trigger event)
1h = Sleep mode
2h = Continuous measure mode
3h = Reserved

7.6.3 SENSOR_CONFIG_1 Register (Offset = 2h) [Reset = 00h]

SENSOR_CONFIG_1 is shown in Table 7-10.

Return to the Summary Table.

Table 7-10 SENSOR_CONFIG_1 Register Field Descriptions
Bit Field Type Reset Description
7-4 MAG_CH_EN R/W 0h Enables data acquisition of the magnetic channel(s).
0h = All magnetic channels of off, default
1h = X channel enabled
2h = Y channel enabled
3h = X, Y channel enabled
4h = Z channel enabled
5h = Z, X channel enabled
6h = Y, Z channel enabled
7h = X, Y, Z channel enabled
8h = XYX channel enabled
9h = YXY channel enabled
Ah = YZY channel enabled
Bh = XZX channel enabled
Ch = X, Y, Z with positive AFE diagnostic check
Dh = X, Y, Z with negative AFE diagnostic check
Eh = Hall resistance check + ADC check
Fh = Hall offset check +ADC check
3-0 RESERVED R 0h Reserved

7.6.4 SENSOR_CONFIG_2 Register (Offset = 3h) [Reset = 00h]

SENSOR_CONFIG_2 is shown in Table 7-11.

Return to the Summary Table.

Table 7-11 SENSOR_CONFIG_2 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0h Reserved
6 THRX_COUNT R/W 0h Number of threshold crossings before the interrupt is asserted.
0h = 1 threshold crossing
1h = 4 threshold crossing
5 MAG_THR_DIR R/W 0h Selects the direction of threshold check. This bit is ignored when THR_HYST > 001b.
0h = sets interrupt for field above the threshold
1h = sets interrupt for field below the threshold
4 MAG_GAIN_CH R/W 0h Selects the axis for magnitude gain correction value entered in MAG_GAIN_CONFIG register.
0h = 1st channel is selected for gain adjustment
1h = 2nd channel is selected for gain adjustment
3-2 ANGLE_EN R/W 0h Enables angle calculation, magnetic gain, and offset corrections between two selected magnetic channels.
0h = No angle calculation, magnitude gain, and offset correction enabled
1h = X 1st, Y 2nd
2h = Y 1st, Z 2nd
3h = X 1st, Z 2nd
1 X_Y_RANGE R/W 0h Select the X and Y axes magnetic range from 2 different options.
0h = ±40mT (TMAG5173A1) or ±133mT (TMAG5173A2), default
1h = ±80mT (TMAG5173A1) or ±266mT (TMAG5173A2)
0 Z_RANGE R/W 0h Select the Z axis magnetic range from 2 different options.
0h = ±40mT (TMAG5173A1) or ±133mT (TMAG5173A2), default
1h = ±80mT (TMAG5173A1) or ±266mT (TMAG5173A2)

7.6.5 X_THR_CONFIG Register (Offset = 4h) [Reset = 00h]

X_THR_CONFIG is shown in Table 7-12.

Return to the Summary Table.

Table 7-12 X_THR_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7-0 X_THR_CONFIG R/W 0h 8-bit, 2's complement X axis threshold code for limit check. The range of possible threshold entrees can be from -128 to 127. The threshold value in mT is calculated for A1 as (40(1+X_Y_RANGE)/128)*X_THR_CONFIG, for A2 as (133(1+X_Y_RANGE)/128)*X_THR_CONFIG. Default 0h means no threshold comparison.

7.6.6 Y_THR_CONFIG Register (Offset = 5h) [Reset = 00h]

Y_THR_CONFIG is shown in Table 7-13.

Return to the Summary Table.

Table 7-13 Y_THR_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7-0 Y_THR_CONFIG R/W 0h 8-bit, 2's complement Y axis threshold code for limit check. The range of possible threshold entrees can be from -128 to 127. The threshold value in mT is calculated for A1 as (40(1+X_Y_RANGE)/128)*Y_THR_CONFIG, for A2 as (133(1+X_Y_RANGE)/128)*Y_THR_CONFIG. Default 0h means no threshold comparison.

7.6.7 Z_THR_CONFIG Register (Offset = 6h) [Reset = 00h]

Z_THR_CONFIG is shown in Table 7-14.

Return to the Summary Table.

Table 7-14 Z_THR_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7-0 Z_THR_CONFIG R/W 0h 8-bit, 2's complement Z axis threshold code for limit check. The range of possible threshold entrees can be from -128 to 127. The threshold value in mT is calculated for A1 as (40(1+Z_RANGE)/128)*Z_THR_CONFIG, for A2 as (133(1+Z_RANGE)/128)*Z_THR_CONFIG. Default 0h means no threshold comparison.

7.6.8 T_CONFIG Register (Offset = 7h) [Reset = 00h]

T_CONFIG is shown in Table 7-15.

Return to the Summary Table.

Table 7-15 T_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7-1 T_THR_CONFIG R/W 0h Temperature threshold code entered by user. The valid temperature threshold ranges are -41C to 170C with the threshold codes for -41C = 1Ah, and 170C = 34h. Resolution is 8-degree C/ LSB. Default 0h means no threshold comparison.
0 T_CH_EN R/W 0h Enables data acquisition of the temperature channel.
0h = Temp channel disabled
1h = Temp channel enabled

7.6.9 INT_CONFIG_1 Register (Offset = 8h) [Reset = 00h]

INT_CONFIG_1 is shown in Table 7-16.

Return to the Summary Table.

Table 7-16 INT_CONFIG_1 Register Field Descriptions
Bit Field Type Reset Description
7 RSLT_INT R/W 0h Enable interrupt response when conversion result is complete.
0h = Interrupt is not asserted when the configured set of conversions are complete
1h = Interrupt is asserted when the configured set of conversions are complete
6 THRSLD_INT R/W 0h Enable interrupt response on a predefined threshold cross.
0h = Interrupt is not asserted when a threshold is crossed
1h = Interrupt is asserted when a threshold is crossed
5 INT_STATE R/W 0h INT interrupt latched or pulsed.
0h = INT interrupt latched until clear by a primary addressing the device
1h = INT interrupt pulse for 10 us
4-2 INT_MODE R/W 0h Interrupt mode select.
0h = No interrupt
1h = Interrupt through INT
2h = Interrupt through INT except when I2C bus is busy.
3h = Interrupt through SCL
4h = Interrupt through SCL except when I2C bus is busy.
5h = Unipolar switch function during continuous measure mode (only one magnetic field conversion support, selects the first magnetic field in X, Y, Z order if multiple thresholds are enabled). This mode overrides any interrupt function (INT trigger is also disabled), and only implements a Hall switch function based off the x_THRX_CONFIG and THR_HYST settings. Select THR_HYST >001b for this mode.
6h = Omnipolar switch function during continuous measure mode (only one magnetic field conversion support, selects the first magnetic field in X, Y, Z order if multiple thresholds are enabled). This mode overrides any interrupt function (INT trigger is also disabled), and only implements a Hall switch function based off the x_THRX_CONFIG and THR_HYST settings. Select THR_HYST >001b for this mode.
7h = Not valid- defaults to 000b mode
1 RESERVED R 0h Reserved
0 MASK_INTB R/W 0h Mask INT pin when INT connected to GND.
0h = INT pin is enabled
1h = INT pin is disabled (for wake-up and trigger functions)

7.6.10 MAG_GAIN_CONFIG Register (Offset = 9h) [Reset = 00h]

MAG_GAIN_CONFIG is shown in Table 7-17.

Return to the Summary Table.

Table 7-17 MAG_GAIN_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7-0 GAIN_VALUE R/W 0h 8-bit gain value determined by a primary to adjust a Hall axis gain. The particular axis is selected based off the settings of MAG_GAIN_CH and ANGLE_EN register bits. The binary 8-bit input is interpreted as a fractional value in between 0 and 1 based off the formula, 'user entered value in decimal/256'. Gain value of 0 is interpreted by the device as 1.

7.6.11 MAG_OFFSET_CONFIG_1 Register (Offset = Ah) [Reset = 00h]

MAG_OFFSET_CONFIG_1 is shown in Table 7-18.

Return to the Summary Table.

Table 7-18 MAG_OFFSET_CONFIG_1 Register Field Descriptions
Bit Field Type Reset Description
7-0 OFFSET_VALUE_1ST R/W 0h 8-bit, 2's complement number entered by a primary to adjust the 1st axis offset during angle calculation. The 1st axis is defined in ANGLE_EN register bits. The range of possible valid entrees in decimal numbers can be -128 to 127. The offset value is calculated by multiplying bit resolution (uT/ LSB) with the entered value.

7.6.12 MAG_OFFSET_CONFIG_2 Register (Offset = Bh) [Reset = 00h]

MAG_OFFSET_CONFIG_2 is shown in Table 7-19.

Return to the Summary Table.

Table 7-19 MAG_OFFSET_CONFIG_2 Register Field Descriptions
Bit Field Type Reset Description
7-0 OFFSET_VALUE_2ND R/W 0h 8-bit, 2's complement number entered by a primary to adjust the 2nd axis offset during angle calculation. The 2nd axis is defined in ANGLE_EN register bits. The range of possible valid entrees in decimal numbers can be -128 to 127. The offset value is calculated by multiplying bit resolution (uT/ LSB) with the entered value.

7.6.13 I2C_ADDRESS Register (Offset = Ch) [Reset = 6Ah]

I2C_ADDRESS is shown in Table 7-20.

Return to the Summary Table.

Table 7-20 I2C_ADDRESS Register Field Descriptions
Bit Field Type Reset Description
7-1 I2C_ADDRESS R/W 35h 7-bit default factory I2C address is loaded from OTP during first power up. Change these bits to a new setting if a new I2C address is required (at each power cycle these bits need to be written again to avoid going back to default factory address).
0 I2C_ADDRESS_UPDATE_EN R/W 0h Enable a new user defined I2C address.
0h = Disable update of I2C address
1h = Enable update of I2C address with bits (7:1)

7.6.14 DEVICE_ID Register (Offset = Dh) [Reset = 04h]

DEVICE_ID is shown in Table 7-21.

Return to the Summary Table.

Table 7-21 DEVICE_ID Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 1h Reserved
1-0 VER R 0h Device version indicator. Reset value of DEVICE_ID depends on the orderable part number.
0h = ±40-mT and ±80-mT range
1h = Reserved
2h = ±133-mT and ±266-mT range
3h = Reserved

7.6.15 MANUFACTURER_ID_LSB Register (Offset = Eh) [Reset = 49h]

MANUFACTURER_ID_LSB is shown in Table 7-22.

Return to the Summary Table.

Table 7-22 MANUFACTURER_ID_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 MANUFACTURER_ID_[7:0] R 49h Unique manufacturer ID LSB bits.

7.6.16 MANUFACTURER_ID_MSB Register (Offset = Fh) [Reset = 54h]

MANUFACTURER_ID_MSB is shown in Table 7-23.

Return to the Summary Table.

Table 7-23 MANUFACTURER_ID_MSB Register Field Descriptions
Bit Field Type Reset Description
7-0 MANUFACTURER_ID_[15:8] R 54h Unique manufacturer ID MSB bits.

7.6.17 T_MSB_RESULT Register (Offset = 10h) [Reset = 00h]

T_MSB_RESULT is shown in Table 7-24.

Return to the Summary Table.

Table 7-24 T_MSB_RESULT Register Field Descriptions
Bit Field Type Reset Description
7-0 T_CH_RESULT [15:8] R 0h T-channel data conversion results, MSB 8 bits.

7.6.18 T_LSB_RESULT Register (Offset = 11h) [Reset = 00h]

T_LSB_RESULT is shown in Table 7-25.

Return to the Summary Table.

Table 7-25 T_LSB_RESULT Register Field Descriptions
Bit Field Type Reset Description
7-0 T_CH_RESULT [7:0] R 0h T-channel data conversion results, LSB 8 bits.

7.6.19 X_MSB_RESULT Register (Offset = 12h) [Reset = 00h]

X_MSB_RESULT is shown in Table 7-26.

Return to the Summary Table.

Table 7-26 X_MSB_RESULT Register Field Descriptions
Bit Field Type Reset Description
7-0 X_CH_RESULT [15:8] R 0h X-channel data conversion results, MSB 8 bits.

7.6.20 X_LSB_RESULT Register (Offset = 13h) [Reset = 00h]

X_LSB_RESULT is shown in Table 7-27.

Return to the Summary Table.

Table 7-27 X_LSB_RESULT Register Field Descriptions
Bit Field Type Reset Description
7-0 X_CH_RESULT [7:0] R 0h X-channel data conversion results, LSB 8 bits.

7.6.21 Y_MSB_RESULT Register (Offset = 14h) [Reset = 00h]

Y_MSB_RESULT is shown in Table 7-28.

Return to the Summary Table.

Table 7-28 Y_MSB_RESULT Register Field Descriptions
Bit Field Type Reset Description
7-0 Y_CH_RESULT [15:8] R 0h Y-channel data conversion results, MSB 8 bits.

7.6.22 Y_LSB_RESULT Register (Offset = 15h) [Reset = 00h]

Y_LSB_RESULT is shown in Table 7-29.

Return to the Summary Table.

Table 7-29 Y_LSB_RESULT Register Field Descriptions
Bit Field Type Reset Description
7-0 Y_CH_RESULT [7:0] R 0h Y-channel data conversion results, LSB 8 bits.

7.6.23 Z_MSB_RESULT Register (Offset = 16h) [Reset = 00h]

Z_MSB_RESULT is shown in Table 7-30.

Return to the Summary Table.

Table 7-30 Z_MSB_RESULT Register Field Descriptions
Bit Field Type Reset Description
7-0 Z_CH_RESULT [15:8] R 0h Z-channel data conversion results, MSB 8 bits.

7.6.24 Z_LSB_RESULT Register (Offset = 17h) [Reset = 00h]

Z_LSB_RESULT is shown in Table 7-31.

Return to the Summary Table.

Table 7-31 Z_LSB_RESULT Register Field Descriptions
Bit Field Type Reset Description
7-0 Z_CH_RESULT [7:0] R 0h Z-channel data conversion results, LSB 8 bits.

7.6.25 CONV_STATUS Register (Offset = 18h) [Reset = 10h]

CONV_STATUS is shown in Table 7-32.

Return to the Summary Table.

Table 7-32 CONV_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-5 SET_COUNT R 0h Rolling count of conversion data sets.
4 POR R/W1CP 1h Device powered up, or experienced power-on-reset. Bit is clear when host writes back '1'.
0h = No POR
1h = POR occurred
3-2 RESERVED R 0h Reserved
1 DIAG_STATUS R 0h Detect any internal diagnostics fail which include VCC UV, internal memory CRC error, INT pin error and internal clock error.
0h = No diagnostic fail
1h = Diagnostic fail detected
0 RESULT_STATUS R 0h Conversion data buffer is ready to be read.
0h = Conversion data not complete
1h = Conversion data complete

7.6.26 ANGLE_RESULT_MSB Register (Offset = 19h) [Reset = 00h]

ANGLE_RESULT_MSB is shown in Table 7-33.

Return to the Summary Table.

Table 7-33 ANGLE_RESULT_MSB Register Field Descriptions
Bit Field Type Reset Description
7-0 ANGLE_RESULT_MSB R 0h Angle measurement result in degree. The data is displayed from 0 to 360 degree in 13 LSB bits after combining the ANGLE_RESULT_MSB and _LSB bits. The 4 LSB bits allocated for fraction of an angle in the format (xxxx/16).

7.6.27 ANGLE_RESULT_LSB Register (Offset = 1Ah) [Reset = 00h]

ANGLE_RESULT_LSB is shown in Table 7-34.

Return to the Summary Table.

Table 7-34 ANGLE_RESULT_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 ANGLE_RESULT_LSB R 0h Angle measurement result in degree. The data is displayed from 0 to 360 degree in 13 LSB bits after combining the ANGLE_RESULT_MSB and _LSB bits. The 4 LSB bits allocated for fraction of an angle in the format (xxxx/16).

7.6.28 MAGNITUDE_RESULT Register (Offset = 1Bh) [Reset = 00h]

MAGNITUDE_RESULT is shown in Table 7-35.

Return to the Summary Table.

Table 7-35 MAGNITUDE_RESULT Register Field Descriptions
Bit Field Type Reset Description
7-0 MAGNITUDE_RESULT R 0h Resultant vector magnitude during angle measurement. This value should be constant during 360-degree on-axis angle measurement. The magnitude in mT can be calculated as (MAGNITUDE_RESULT*256)/(LSB/mT) where the LSB/mT is calculated in 16-bit format as specified in the magnetic characteristics table.

7.6.29 DEVICE_STATUS Register (Offset = 1Ch) [Reset = 10h]

DEVICE_STATUS is shown in Table 7-36.

Return to the Summary Table.

Table 7-36 DEVICE_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R 0h Reserved
4 INTB_RB R 1h Indicates the level that the device is reading back from INT pin. The reset value of DEVICE_STATUS depends on the status of the INT pin at power-up.
0h = INT pin driven low
1h = INT pin status high
3 OSC_ER R/W1CP 0h Indicates if Oscillator error is detected. Bit is clear when host writes back '1'.
0h = No oscillator error detected
1h = Oscillator error detected
2 INT_ER R/W1CP 0h Indicates if INT pin error is detected. Bit is clear when host writes back '1'.
0h = No INT error detected
1h = INT error detected
1 OTP_CRC_ER R/W1CP 0h Indicates if OTP CRC error is detected. Bit is clear when host writes back '1'.
0h = No OTP CRC error detected
1h = OTP CRC error detected
0 VCC_UV_ER R/W1CP 0h Indicates if VCC undervoltage was detected. Bit is clear when host writes back '1'.
0h = No VCC UV detected
1h = VCC UV detected