SLASE75D August   2015  – September 2017 TMDS181

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Electrical Characteristics
    6. 6.6  TMDS Differential Input Electrical Characteristics
    7. 6.7  TMDS Differential Output Electrical Characteristics
    8. 6.8  DDC, I2C, HPD, and ARC Electrical Characteristics
    9. 6.9  Power-Up and Operation Timing Requirements
    10. 6.10 TMDS Switching Characteristics
    11. 6.11 HPD Switching Characteristics
    12. 6.12 DDC and I2C Switching Characteristics
    13. 6.13 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reset Implementation
      2. 8.3.2  Operation Timing
      3. 8.3.3  Swap and Polarity Working
      4. 8.3.4  TMDS Inputs
      5. 8.3.5  TMDS Inputs Debug Tools
      6. 8.3.6  Receiver Equalizer
      7. 8.3.7  Input Signal Detect Block
      8. 8.3.8  Audio Return Channel
      9. 8.3.9  Transmitter Impedance Control
      10. 8.3.10 TMDS Outputs
      11. 8.3.11 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Training for HDMI2.0a Data Rate Monitor
      4. 8.4.4 DDC Functional Description
      5. 8.4.5 Mode Selection Functional Description
    5. 8.5 Register Maps
      1. 8.5.1 Local I2C Overview
      2. 8.5.2 Local I2C Control Bit Access TAG Convention
      3. 8.5.3 CSR Bit Field Definitions
        1. 8.5.3.1 ID Registers
        2. 8.5.3.2 MISC CONTROL Register
        3. 8.5.3.3 Equalization Control Register
        4. 8.5.3.4 RX PATTERN VERIFIER CONTROL/STATUS Register
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Source Side Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sink Side Application
      3. 9.2.3 Application Chain Showing DDC Connections
        1. 9.2.3.1 Detailed Design Procedure
          1. 9.2.3.1.1 DDC Pullup Resistors
          2. 9.2.3.1.2 Compliance Testing
            1. 9.2.3.1.2.1 Pin Strapping Configuration for HDMI2.0a and HDMI1.4b
            2. 9.2.3.1.2.2 I2C Control for HDMI2.0a and HDMI1.4b
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout

Layout Guidelines

For the TMDS181 on a high-K board: It is required to solder the PowerPAD™ onto the thermal land to ground. A thermal land is the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the TMDS181 can operate over the full temperature range by soldering the PowerPAD onto the thermal land.

On a low-K board: For the device to operate across the temperature range on a low-K board, the designer must use a 1-oz Cu trace connecting the GND pins to the thermal land. A simulation shows RθJA = 100.84°C/W allowing 545 mW power dissipation at 70°C ambient temperature. A general PCB design guide for PowerPAD packages is provided in PowerPAD Thermally Enhanced Package, SLMA002. TI recommends using at a minimum a four-layer stack to accomplish a low-EMI PCB design. TI recommends six layers as the TMDS181 is a two-voltage-rail device.

  • Routing the high-speed TMDS traces on the top layer avoids the use of vias (and their discontinuities) and allows for clean interconnects from the HDMI connectors to the retimer inputs and outputs. It is important to match the electrical length of these high-speed traces to minimize both inter-pair and intra-pair skew.
  • Placing a solid ground plane next to the high-speed single layer establishes controlled impedance for transmission link interconnects and provides an excellent low-inductance path for the return current flow.
  • Placing a power plane next to the ground plane creates an additional high-frequency bypass capacitance.
  • Routing slower-speed control signals on the bottom layer allows for greater flexibility because these signal links usually have margin to tolerate discontinuities such as vias.
  • If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. Also, the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.
TMDS181 TMDS181I recmd_stack_LASE75.gif Figure 38. Recommended 4- or 6-Layer PCB Stack

Layout Example

TMDS181 TMDS181I layout_ex_LASE75.gif
If ARC is not used, tie a 500 kΩ resistor to GND at the SPDIF_IN pin.
The 55 Ω resistor to GND on the ARC_OUT pin is implementation specific and may not be needed if it is already implemented elsewhere.
Figure 39. Layout Example – Source Side