JAJSOO3A October   2014  – June 2022 TMP75B-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 Temperature Limits and Alert
      3. 7.3.3 Serial Interface
        1. 7.3.3.1  Bus Overview
        2. 7.3.3.2  Serial Bus Address
        3. 7.3.3.3  Writing and Reading Operation
        4. 7.3.3.4  Target-Mode Operations
          1. 7.3.3.4.1 Target Receiver Mode:
          2. 7.3.3.4.2 Target Transmitter Mode:
        5. 7.3.3.5  SMBus Alert Function
        6. 7.3.3.6  General Call
        7. 7.3.3.7  High-Speed (Hs) Mode
        8. 7.3.3.8  Timeout Function
        9. 7.3.3.9  Two-Wire Timing
        10. 7.3.3.10 Two-Wire Timing Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous-Conversion Mode
      2. 7.4.2 Shutdown Mode
      3. 7.4.3 One-Shot Mode
    5. 7.5 Programming
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3.9 Two-Wire Timing

The TMP75B-Q1 is two-wire and SMBus compatible. Figure 7-2 to Figure 7-5 describe the various operations on the TMP75B-Q1. Parameters for Figure 7-2 are defined in Table 7-3. Bus definitions are:

    Bus IdleBoth SDA and SCL lines remain high.
    Start Data TransferA change in the state of the SDA line, from high to low, while the SCL line is high defines a start condition. Each data transfer is initiated with a start condition.
    Stop Data TransferA change in the state of the SDA line from low to high while the SCL line is high defines a stop condition. Each data transfer is terminated with a repeated start or stop condition.
    Data TransferThe number of data bytes transferred between a start and a stop condition is not limited, and is determined by the controller device.

    The receiver acknowledges the transfer of data. It is also possible to use the TMP75B-Q1 for single-byte updates. To update only the MS byte, terminate communication by issuing a start or stop condition on the bus.

    AcknowledgeEach receiving device, when addressed, must generate an acknowledge bit.

    A device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into account. When a controller receives data, the termination of the data transfer can be signaled by the controller generating a not-acknowledge (1) on the last byte transmitted by the target.

Table 7-3 Timing Diagram Requirements
PARAMETERFAST MODEHIGH-SPEED MODEUNIT
MINMAXMINMAX
f(SCL)SCL operating frequencyVS ≥ 1.8 V0.0010.40.0013MHz
VS < 1.8 V0.0010.40.0012.5MHz
t(BUF)Bus free time between stop and start conditionsVS ≥ 1.8 V1300160ns
VS < 1.8 V1300260ns
t(HDSTA)Hold time after repeated start condition.
After this period, the first clock is generated.		600160ns
t(SUSTA)Repeated start condition setup time600160ns
t(SUSTO)Stop condition setup time600160ns
t(HDDAT)Data hold timeVS ≥ 1.8 V09000100ns
VS < 1.8 V09000140ns
t(SUDAT)Data setup timeVS ≥ 1.8 V10010ns
VS < 1.8 V10020ns
t(LOW)SCL clock low periodVS ≥ 1.8 V1300190ns
VS < 1.8 V1300240ns
t(HIGH)SCL clock high period60060ns
tR(SDA), tF(SDA)Data rise and fall time30080ns
tR(SCL), tF(SCL)Clock rise and fall time30040ns
tRClock and data rise time for SCLK ≤ 100 kHz1000ns