JAJSIR1B March   2020  – December 2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1. 3.1 機能ブロック図
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pin Multiplexing
      1. 6.4.1 GPIO Muxed Pins
        1. 6.4.1.1 GPIO Muxed Pins Table
      2. 6.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 6.4.3 GPIO Input X-BAR
      4. 6.4.4 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 6.5 Pins With Internal Pullup and Pulldown
    6. 6.6 Connections for Unused Pins
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5.     Supply Voltages
    6. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption
      2. 7.5.2 Operating Mode Test Description
      3. 7.5.3 Current Consumption Graphs
      4. 7.5.4 Reducing Current Consumption
        1. 7.5.4.1 Typical Current Reduction per Disabled Peripheral
    7. 7.6  Electrical Characteristics
    8. 7.7  Thermal Resistance Characteristics for PN Package
    9. 7.8  Thermal Resistance Characteristics for PM Package
    10. 7.9  Thermal Resistance Characteristics for PT Package
    11. 7.10 Thermal Design Considerations
    12. 7.11 System
      1. 7.11.1 Power Management
        1. 7.11.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
        2. 7.11.1.2 Power Sequencing
        3. 7.11.1.3 Power-On Reset (POR)
        4. 7.11.1.4 Brownout Reset (BOR)
      2. 7.11.2 Reset Timing
        1. 7.11.2.1 Reset Sources
        2. 7.11.2.2 Reset Electrical Data and Timing
          1. 7.11.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.11.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.11.2.2.3 Reset Timing Diagrams
      3. 7.11.3 Clock Specifications
        1. 7.11.3.1 Clock Sources
        2. 7.11.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.11.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.11.3.2.1.1 Input Clock Frequency
            2. 7.11.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.11.3.2.1.3 X1 Timing Requirements
            4. 7.11.3.2.1.4 APLL Characteristics
            5. 7.11.3.2.1.5 XCLKOUT Switching Characteristics
            6. 7.11.3.2.1.6 Internal Clock Frequencies
        3. 7.11.3.3 Input Clocks and PLLs
        4. 7.11.3.4 Crystal Oscillator
          1. 7.11.3.4.1 Crystal Oscillator Parameters
          2. 7.11.3.4.2 Crystal Oscillator Electrical Characteristics
        5. 7.11.3.5 Internal Oscillators
          1. 7.11.3.5.1 INTOSC Characteristics
      4. 7.11.4 Flash Parameters
      5. 7.11.5 Emulation/JTAG
        1. 7.11.5.1 JTAG Electrical Data and Timing
          1. 7.11.5.1.1 JTAG Timing Requirements
          2. 7.11.5.1.2 JTAG Switching Characteristics
          3. 7.11.5.1.3 JTAG Timing Diagram
        2. 7.11.5.2 cJTAG Electrical Data and Timing
          1. 7.11.5.2.1 cJTAG Timing Requirements
          2. 7.11.5.2.2 cJTAG Switching Characteristics
          3. 7.11.5.2.3 cJTAG Timing Diagram
      6. 7.11.6 GPIO Electrical Data and Timing
        1. 7.11.6.1 GPIO – Output Timing
          1. 7.11.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.11.6.2 GPIO – Input Timing
          1. 7.11.6.2.1 General-Purpose Input Timing Requirements
          2. 7.11.6.2.2 Sampling Mode
        3. 7.11.6.3 Sampling Window Width for Input Signals
      7. 7.11.7 Interrupts
        1. 7.11.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.11.7.1.1 External Interrupt Timing Requirements
          2. 7.11.7.1.2 External Interrupt Switching Characteristics
          3. 7.11.7.1.3 External Interrupt Timing
      8. 7.11.8 Low-Power Modes
        1. 7.11.8.1 Clock-Gating Low-Power Modes
        2. 7.11.8.2 Low-Power Mode Wake-up Timing
          1. 7.11.8.2.1 IDLE Mode Timing Requirements
          2. 7.11.8.2.2 IDLE Mode Switching Characteristics
          3. 7.11.8.2.3 IDLE Entry and Exit Timing Diagram
          4. 7.11.8.2.4 STANDBY Mode Timing Requirements
          5. 7.11.8.2.5 STANDBY Mode Switching Characteristics
          6. 7.11.8.2.6 STANDBY Entry and Exit Timing Diagram
          7. 7.11.8.2.7 HALT Mode Timing Requirements
          8. 7.11.8.2.8 HALT Mode Switching Characteristics
          9. 7.11.8.2.9 HALT Entry and Exit Timing Diagram
    13. 7.12 Analog Peripherals
      1.      Analog Pins and Internal Connections
      2.      Analog Signal Descriptions
      3. 7.12.1 Analog-to-Digital Converter (ADC)
        1. 7.12.1.1 ADC Configurability
          1. 7.12.1.1.1 Signal Mode
        2. 7.12.1.2 ADC Electrical Data and Timing
          1. 7.12.1.2.1 ADC Operating Conditions
          2. 7.12.1.2.2 ADC Characteristics
          3. 7.12.1.2.3 ADC Input Model
          4. 7.12.1.2.4 ADC Timing Diagrams
      4. 7.12.2 Temperature Sensor
        1. 7.12.2.1 Temperature Sensor Electrical Data and Timing
          1. 7.12.2.1.1 Temperature Sensor Characteristics
      5. 7.12.3 Comparator Subsystem (CMPSS)
        1. 7.12.3.1 CMPSS Electrical Data and Timing
          1. 7.12.3.1.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 7.12.3.1.2 CMPSS DAC Static Electrical Characteristics
          4. 7.12.3.1.3 CMPSS Illustrative Graphs
    14. 7.13 Control Peripherals
      1. 7.13.1 Enhanced Pulse Width Modulator (ePWM)
        1. 7.13.1.1 Control Peripherals Synchronization
        2. 7.13.1.2 ePWM Electrical Data and Timing
          1. 7.13.1.2.1 ePWM Timing Requirements
          2. 7.13.1.2.2 ePWM Switching Characteristics
          3. 7.13.1.2.3 Trip-Zone Input Timing
            1. 7.13.1.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.13.1.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.13.1.3.1 External ADC Start-of-Conversion Switching Characteristics
      2. 7.13.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.13.2.1 HRPWM Electrical Data and Timing
          1. 7.13.2.1.1 High-Resolution PWM Characteristics
      3. 7.13.3 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 7.13.3.1 High-Resolution Capture (HRCAP)
        2.       eCAP and HRCAP Block Diagram
        3. 7.13.3.2 eCAP/HRCAP Synchronization
        4. 7.13.3.3 eCAP Electrical Data and Timing
          1. 7.13.3.3.1 eCAP Timing Requirements
          2. 7.13.3.3.2 eCAP Switching Characteristics
        5. 7.13.3.4 HRCAP Electrical Data and Timing
          1. 7.13.3.4.1 HRCAP Switching Characteristics
          2.        HRCAP Figure and Graph
      4. 7.13.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.13.4.1 eQEP Electrical Data and Timing
          1. 7.13.4.1.1 eQEP Timing Requirements
          2. 7.13.4.1.2 eQEP Switching Characteristics
    15. 7.14 Communications Peripherals
      1. 7.14.1 Controller Area Network (CAN)
      2. 7.14.2 Inter-Integrated Circuit (I2C)
        1. 7.14.2.1 I2C Electrical Data and Timing
          1. 7.14.2.1.1 I2C Timing Requirements
          2. 7.14.2.1.2 I2C Switching Characteristics
          3. 7.14.2.1.3 I2C Timing Diagram
      3. 7.14.3 Power Management Bus (PMBus) Interface
        1. 7.14.3.1 PMBus Electrical Data and Timing
          1. 7.14.3.1.1 PMBus Electrical Characteristics
          2. 7.14.3.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.14.3.1.3 PMBus Standard Mode Switching Characteristics
      4. 7.14.4 Serial Communications Interface (SCI)
      5. 7.14.5 Serial Peripheral Interface (SPI)
        1. 7.14.5.1 SPI Master Mode Timings
          1. 7.14.5.1.1 SPI Master Mode Timing Requirements
          2. 7.14.5.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
          3. 7.14.5.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          4. 7.14.5.1.4 SPI Master Mode Timing Diagrams
        2. 7.14.5.2 SPI Slave Mode Timings
          1. 7.14.5.2.1 SPI Slave Mode Timing Requirements
          2. 7.14.5.2.2 SPI Slave Mode Switching Characteristics
          3. 7.14.5.2.3 SPI Slave Mode Timing Diagrams
      6. 7.14.6 Local Interconnect Network (LIN)
      7. 7.14.7 Fast Serial Interface (FSI)
        1. 7.14.7.1 FSI Transmitter
          1. 7.14.7.1.1 FSITX Electrical Data and Timing
            1. 7.14.7.1.1.1 FSITX Switching Characteristics
            2. 7.14.7.1.1.2 FSITX Timings
        2. 7.14.7.2 FSI Receiver
          1. 7.14.7.2.1 FSIRX Electrical Data and Timing
            1. 7.14.7.2.1.1 FSIRX Timing Requirements
            2. 7.14.7.2.1.2 FSIRX Switching Characteristics
            3. 7.14.7.2.1.3 FSIRX Timings
        3. 7.14.7.3 FSI SPI Compatibility Mode
          1. 7.14.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.14.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 7.14.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 7.14.8 Host Interface Controller (HIC)
        1. 7.14.8.1 HIC Electrical Data and Timing
          1. 7.14.8.1.1 HIC Timing Requirements
          2. 7.14.8.1.2 HIC Switching Characteristics
          3. 7.14.8.1.3 HIC Timing Diagrams
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Memory
      1. 8.3.1 Memory Map
        1. 8.3.1.1 Dedicated RAM (Mx RAM)
        2. 8.3.1.2 Local Shared RAM (LSx RAM)
        3. 8.3.1.3 Global Shared RAM (GSx RAM)
      2. 8.3.2 Flash Memory Map
        1. 8.3.2.1 Addresses of Flash Sectors
      3. 8.3.3 Peripheral Registers Memory Map
    4. 8.4  Identification
    5. 8.5  Bus Architecture – Peripheral Connectivity
    6. 8.6  C28x Processor
      1. 8.6.1 Floating-Point Unit (FPU)
      2. 8.6.2 Fast Integer Division Unit
      3. 8.6.3 Trigonometric Math Unit (TMU)
      4. 8.6.4 VCRC Unit
    7. 8.7  Embedded Real-Time Analysis and Diagnostic (ERAD)
    8. 8.8  Background CRC-32 (BGCRC)
    9. 8.9  Direct Memory Access (DMA)
    10. 8.10 Device Boot Modes
      1. 8.10.1 Device Boot Configurations
        1. 8.10.1.1 Configuring Boot Mode Pins
        2. 8.10.1.2 Configuring Boot Mode Table Options
      2. 8.10.2 GPIO Assignments
    11. 8.11 Dual Code Security Module
    12. 8.12 Watchdog
    13. 8.13 C28x Timers
    14. 8.14 Dual-Clock Comparator (DCC)
      1. 8.14.1 特長
      2. 8.14.2 Mapping of DCCx (DCC0 and DCC1) Clock Source Inputs
    15. 8.15 Configurable Logic Block (CLB)
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Markings
    4. 10.4 Tools and Software
    5. 10.5 Documentation Support
    6. 10.6 サポート・リソース
    7. 10.7 Trademarks
    8. 10.8 静電気放電に関する注意事項
    9. 10.9 用語集
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.11.4 Flash Parameters

Table 7-4 lists the minimum required Flash wait states with different clock sources and frequencies. Wait state is the value set in register FRDCNTL[RWAIT].

Table 7-4 Minimum Required Flash Wait States with Different Clock Sources and Frequencies
CPUCLK (MHz) EXTERNAL OSCILLATOR OR CRYSTAL INTOSC1 OR INTOSC2
NORMAL OPERATION BANK OR PUMP SLEEP(1) NORMAL OPERATION BANK OR PUMP SLEEP(1)
97 < CPUCLK ≤ 100 4 4 5
80 < CPUCLK ≤ 97 4
77 < CPUCLK ≤ 80 3 3 4
60 < CPUCLK ≤ 77 3
58 < CPUCLK ≤ 60 2 2 3
40 < CPUCLK ≤ 58 2
38 < CPUCLK ≤ 40 1 1 2
20 < CPUCLK ≤ 38 1
19 < CPUCLK ≤ 20 0 0 1
CPUCLK ≤ 19 0
(1) Flash SLEEP operations require an extra wait state when using INTOSC as the clock source for the frequency ranges indicated. Any wait state FRDCNTL[RWAIT] change must be made before beginning a SLEEP mode operation. This setting impacts both flash banks.

The F28002x devices have an improved 128-bit prefetch buffer that provides high flash code execution efficiency across wait states. Figure 7-15 and Figure 7-16 illustrate typical efficiency across wait-state settings compared to previous-generation devices with a 64-bit prefetch buffer. Wait-state execution efficiency with a prefetch buffer will depend on how many branches are present in application software. Two examples of linear code and if-then-else code are provided.

GUID-62BC42CD-C827-4B12-A92D-0EED4A398DB2-low.gifFigure 7-15 Application Code With Heavy 32-Bit Floating-Point Math Instructions
GUID-B739B7EF-303A-4840-8E86-8EA0C12E9C6F-low.gifFigure 7-16 Application Code With 16-Bit If-Else Instructions

Table 7-5 lists the Flash parameters.

Table 7-5 Flash Parameters 
PARAMETER MIN TYP MAX UNIT
Program Time(1) 128 data bits + 16 ECC bits 150 300 µs
8KB sector 50 100 ms
EraseTime(2)(3) at < 25 cycles 8KB sector 15 100 ms
EraseTime(2)(3) at 1000 cycles 8KB sector 25 350 ms
EraseTime(2)(3) at 2000 cycles 8KB sector 30 600 ms
EraseTime(2)(3) at 20K cycles 8KB sector 120 4000 ms
Nwec Write/Erase Cycles per sector 20000 cycles
Nwec Write/Erase Cycles for entire Flash (combined all sectors) 100000 cycles
tretention  Data retention duration at TJ = 85oC 20 years
(1) Program time is at the maximum device frequency.  Program time includes overhead of the flash state machine but does not include the time to transfer the following into RAM:
• Code that uses flash API to program the flash        
• Flash API itself            
• Flash data to be programmed            
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations.
Note:

The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit word may only be programmed once per write/erase cycle.

The DCSM OTP programming must be aligned to 128-bit address boundaries and each 128-bit word may only be programmed once. The exceptions are:

  1. The DCSM Zx-LINKPOINTER1 and Zx-LINKPOINTER2 values in the DCSM OTP should be programmed together, and may be programmed 1 bit at a time as required by the DCSM operation.
  2. The DCSM Zx-LINKPOINTER3 values in the DCSM OTP may be programmed 1 bit at a time on a 64-bit boundary to separate it from Zx-PSWDLOCK, which must only be programmed once.