JAJSE04E January   2017  – April 2020 TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280049 , TMS320F280049C

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 Analog Signals
      2. 4.3.2 Digital Signals
      3. 4.3.3 Power and Ground
      4. 4.3.4 Test, JTAG, and Reset
    4. 4.4 Pin Multiplexing
      1. 4.4.1 GPIO Muxed Pins
      2. 4.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 4.4.3 GPIO Input X-BAR
      4. 4.4.4 GPIO Output X-BAR and ePWM X-BAR
    5. 4.5 Pins With Internal Pullup and Pulldown
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 System Current Consumption (External Supply)
      2. Table 5-2 System Current Consumption (Internal VREG)
      3. Table 5-3 System Current Consumption (DCDC)
      4. 5.5.1     Operating Mode Test Description
      5. 5.5.2     Current Consumption Graphs
      6. 5.5.3     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PZ Package
      2. 5.7.2 PM Package
      3. 5.7.3 RSH Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  System
      1. 5.9.1 Power Management
        1. 5.9.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
        2. 5.9.1.2 Internal 1.2-V Switching Regulator (DC-DC)
          1. 5.9.1.2.1 PCB Layout and Component Guidelines
            1. Table 5-8 Recommended External Components
        3. 5.9.1.3 Deciding Between the LDO and the DC-DC
        4. 5.9.1.4 Power Sequencing
        5. 5.9.1.5 Power-On Reset (POR)
        6. 5.9.1.6 Brownout Reset (BOR)
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Sources
        2. 5.9.2.2 Reset Electrical Data and Timing
          1. Table 5-10 Reset (XRSn) Timing Requirements
          2. Table 5-11 Reset (XRSn) Switching Characteristics
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1 Clock Sources
        2. 5.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-13 Input Clock Frequency
            2. Table 5-14 XTAL Oscillator Characteristics
            3. Table 5-15 X1 Timing Requirements
            4. Table 5-16 PLL Lock Times
          2. 5.9.3.2.2 Internal Clock Frequencies
            1. Table 5-17 Internal Clock Frequencies
          3. 5.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 5-18 XCLKOUT Switching Characteristics
        3. 5.9.3.3 Input Clocks and PLLs
        4. 5.9.3.4 Crystal Oscillator
          1. Table 5-19 Crystal Oscillator Parameters
          2. Table 5-21 Crystal Oscillator Electrical Characteristics
        5. 5.9.3.5 Internal Oscillators
          1. Table 5-22 INTOSC Characteristics
      4. 5.9.4 Flash Parameters
      5. 5.9.5 Emulation/JTAG
        1. 5.9.5.1 JTAG Electrical Data and Timing
          1. Table 5-25 JTAG Timing Requirements
          2. Table 5-26 JTAG Switching Characteristics
        2. 5.9.5.2 cJTAG Electrical Data and Timing
          1. Table 5-27 cJTAG Timing Requirements
          2. Table 5-28 cJTAG Switching Characteristics
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO – Output Timing
          1. Table 5-29 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO – Input Timing
          1. Table 5-30 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
      7. 5.9.7 Interrupts
        1. 5.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-31 External Interrupt Timing Requirements
          2. Table 5-32 External Interrupt Switching Characteristics
      8. 5.9.8 Low-Power Modes
        1. 5.9.8.1 Clock-Gating Low-Power Modes
        2. 5.9.8.2 Low-Power Mode Wake-up Timing
          1. Table 5-34 IDLE Mode Timing Requirements
          2. Table 5-35 IDLE Mode Switching Characteristics
          3. Table 5-36 HALT Mode Timing Requirements
          4. Table 5-37 HALT Mode Switching Characteristics
    10. 5.10 Analog Peripherals
      1. 5.10.1 Analog-to-Digital Converter (ADC)
        1. 5.10.1.1 ADC Configurability
          1. 5.10.1.1.1 Signal Mode
        2. 5.10.1.2 ADC Electrical Data and Timing
          1. Table 5-41 ADC Operating Conditions
          2. Table 5-42 ADC Characteristics
          3. 5.10.1.2.1 ADC Input Model
          4. 5.10.1.2.2 ADC Timing Diagrams
      2. 5.10.2 Programmable Gain Amplifier (PGA)
        1. 5.10.2.1 PGA Electrical Data and Timing
          1. Table 5-47 PGA Operating Conditions
          2. Table 5-48 PGA Characteristics
          3. 5.10.2.1.1 PGA Typical Characteristics Graphs
      3. 5.10.3 Temperature Sensor
        1. 5.10.3.1 Temperature Sensor Electrical Data and Timing
          1. Table 5-49 Temperature Sensor Characteristics
      4. 5.10.4 Buffered Digital-to-Analog Converter (DAC)
        1. 5.10.4.1 Buffered DAC Electrical Data and Timing
          1. Table 5-50 Buffered DAC Operating Conditions
          2. Table 5-51 Buffered DAC Electrical Characteristics
          3. 5.10.4.1.1 Buffered DAC Illustrative Graphs
          4. 5.10.4.1.2 Buffered DAC Typical Characteristics Graphs
      5. 5.10.5 Comparator Subsystem (CMPSS)
        1. 5.10.5.1 CMPSS Electrical Data and Timing
          1. Table 5-52 Comparator Electrical Characteristics
          2. Table 5-53 CMPSS DAC Static Electrical Characteristics
          3. 5.10.5.1.1 CMPSS Illustrative Graphs
    11. 5.11 Control Peripherals
      1. 5.11.1 Enhanced Capture (eCAP)
        1. 5.11.1.1 eCAP Electrical Data and Timing
          1. Table 5-54 eCAP Timing Requirements
          2. Table 5-55 eCAP Switching Charcteristics
      2. 5.11.2 High-Resolution Capture Submodule (HRCAP6–HRCAP7)
        1. 5.11.2.1 HRCAP Electrical Data and Timing
          1. Table 5-56 HRCAP Switching Characteristics
      3. 5.11.3 Enhanced Pulse Width Modulator (ePWM)
        1. 5.11.3.1 Control Peripherals Synchronization
        2. 5.11.3.2 ePWM Electrical Data and Timing
          1. Table 5-57 ePWM Timing Requirements
          2. Table 5-58 ePWM Switching Characteristics
          3. 5.11.3.2.1 Trip-Zone Input Timing
            1. Table 5-59 Trip-Zone Input Timing Requirements
        3. 5.11.3.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-60 External ADC Start-of-Conversion Switching Characteristics
      4. 5.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.11.4.1 HRPWM Electrical Data and Timing
          1. Table 5-61 High-Resolution PWM Characteristics
      5. 5.11.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.11.5.1 eQEP Electrical Data and Timing
          1. Table 5-62 eQEP Timing Requirements
          2. Table 5-63 eQEP Switching Characteristics
      6. 5.11.6 Sigma-Delta Filter Module (SDFM)
        1. 5.11.6.1 SDFM Electrical Data and Timing
          1. Table 5-64 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 5.11.6.2 SDFM Electrical Data and Timing (Synchronized GPIO)
          1. Table 5-65 SDFM Timing Requirements When Using Synchronized GPIO (SYNC) Option
    12. 5.12 Communications Peripherals
      1. 5.12.1 Controller Area Network (CAN)
      2. 5.12.2 Inter-Integrated Circuit (I2C)
        1. 5.12.2.1 I2C Electrical Data and Timing
          1. Table 5-66 I2C Timing Requirements
          2. Table 5-67 I2C Switching Characteristics
      3. 5.12.3 Power Management Bus (PMBus) Interface
        1. 5.12.3.1 PMBus Electrical Data and Timing
          1. Table 5-68 PMBus Electrical Characteristics
          2. Table 5-69 PMBus Fast Mode Switching Characteristics
          3. Table 5-70 PMBus Standard Mode Switching Characteristics
      4. 5.12.4 Serial Communications Interface (SCI)
      5. 5.12.5 Serial Peripheral Interface (SPI)
        1. 5.12.5.1 SPI Electrical Data and Timing
          1. 5.12.5.1.1 Non-High-Speed Master Mode Timings
            1. Table 5-71 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-72 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-73 SPI Master Mode Timing Requirements
          2. 5.12.5.1.2 Non-High-Speed Slave Mode Timings
            1. Table 5-74 SPI Slave Mode Switching Characteristics
            2. Table 5-75 SPI Slave Mode Timing Requirements
          3. 5.12.5.1.3 High-Speed Master Mode Timings
            1. Table 5-76 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-77 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-78 SPI High-Speed Master Mode Timing Requirements
          4. 5.12.5.1.4 High-Speed Slave Mode Timings
            1. Table 5-79 SPI High-Speed Slave Mode Switching Characteristics
            2. Table 5-80 SPI High-Speed Slave Mode Timing Requirements
      6. 5.12.6 Local Interconnect Network (LIN)
      7. 5.12.7 Fast Serial Interface (FSI)
        1. 5.12.7.1 FSI Transmitter
          1. 5.12.7.1.1 FSITX Electrical Data and Timing
            1. Table 5-81 FSITX Switching Characteristics
        2. 5.12.7.2 FSI Receiver
          1. 5.12.7.2.1 FSIRX Electrical Data and Timing
            1. Table 5-82 FSIRX Switching Characteristics
            2. Table 5-83 FSIRX Timing Requirements
        3. 5.12.7.3 FSI SPI Compatibility Mode
          1. 5.12.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. Table 5-84 FSITX SPI Signaling Mode Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Memory
      1. 6.3.1 C28x Memory Map
      2. 6.3.2 Control Law Accelerator (CLA) ROM Memory Map
      3. 6.3.3 Flash Memory Map
      4. 6.3.4 Peripheral Registers Memory Map
      5. 6.3.5 Memory Types
        1. 6.3.5.1 Dedicated RAM (Mx RAM)
        2. 6.3.5.2 Local Shared RAM (LSx RAM)
        3. 6.3.5.3 Global Shared RAM (GSx RAM)
        4. 6.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 6.4  Identification
    5. 6.5  Bus Architecture – Peripheral Connectivity
    6. 6.6  C28x Processor
      1. 6.6.1 Embedded Real-Time Analysis and Diagnostic (ERAD)
      2. 6.6.2 Floating-Point Unit (FPU)
      3. 6.6.3 Trigonometric Math Unit (TMU)
      4. 6.6.4 Viterbi, Complex Math and CRC Unit (VCU-I)
    7. 6.7  Control Law Accelerator (CLA)
    8. 6.8  Direct Memory Access (DMA)
    9. 6.9  Boot ROM and Peripheral Booting
      1. 6.9.1 Configuring Alternate Boot Mode Select Pins
      2. 6.9.2 Configuring Alternate Boot Mode Options
      3. 6.9.3 GPIO Assignments
    10. 6.10 Dual Code Security Module
    11. 6.11 Watchdog
    12. 6.12 Configurable Logic Block (CLB)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 デバイスおよび開発ツールの項目表記
    2. 8.2 マーキング
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Support Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.4.1 GPIO Muxed Pins

Table 4-6 lists the GPIO muxed pins. The default mode for each GPIO pin is the GPIO function, except GPIO35 and GPIO37, which default to TDI and TDO, respectively. Secondary functions can be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be configured before the GPyMUXn to avoid transient pulses on GPIOs from alternate mux selections. Columns that are not shown and blank cells are reserved GPIO Mux settings.

NOTE

GPIO20, GPIO21, and GPIO41 to GPIO55 are not available on any packages. Boot ROM enables pullups on these pins. For more details, see Section 4.5.

Table 4-6 GPIO Muxed Pins

0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15
GPIO0 EPWM1_A I2CA_SDA
GPIO1 EPWM1_B I2CA_SCL
GPIO2 EPWM2_A OUTPUTXBAR1 PMBUSA_SDA SCIA_TX FSIRXA_D1
GPIO3 EPWM2_B OUTPUTXBAR2 OUTPUTXBAR2 PMBUSA_SCL SPIA_CLK SCIA_RX FSIRXA_D0
GPIO4 EPWM3_A OUTPUTXBAR3 CANA_TX FSIRXA_CLK
GPIO5 EPWM3_B OUTPUTXBAR3 CANA_RX SPIA_STE FSITXA_D1
GPIO6 EPWM4_A OUTPUTXBAR4 SYNCOUT EQEP1_A CANB_TX SPIB_SOMI FSITXA_D0
GPIO7 EPWM4_B OUTPUTXBAR5 EQEP1_B CANB_RX SPIB_SIMO FSITXA_CLK
GPIO8 EPWM5_A CANB_TX ADCSOCAO EQEP1_STROBE SCIA_TX SPIA_SIMO I2CA_SCL FSITXA_D1
GPIO9 EPWM5_B SCIB_TX OUTPUTXBAR6 EQEP1_INDEX SCIA_RX SPIA_CLK FSITXA_D0
GPIO10 EPWM6_A CANB_RX ADCSOCBO EQEP1_A SCIB_TX SPIA_SOMI I2CA_SDA FSITXA_CLK
GPIO11 EPWM6_B SCIB_RX OUTPUTXBAR7 EQEP1_B SCIB_RX SPIA_STE FSIRXA_D1
GPIO12 EPWM7_A CANB_TX EQEP1_STROBE SCIB_TX PMBUSA_CTL FSIRXA_D0
GPIO13 EPWM7_B CANB_RX EQEP1_INDEX SCIB_RX PMBUSA_ALERT FSIRXA_CLK
GPIO14 EPWM8_A SCIB_TX OUTPUTXBAR3 PMBUSA_SDA SPIB_CLK EQEP2_A
GPIO15 EPWM8_B SCIB_RX OUTPUTXBAR4 PMBUSA_SCL SPIB_STE EQEP2_B
GPIO16 SPIA_SIMO CANB_TX OUTPUTXBAR7 EPWM5_A SCIA_TX SD1_D1 EQEP1_STROBE PMBUSA_SCL XCLKOUT
GPIO17 SPIA_SOMI CANB_RX OUTPUTXBAR8 EPWM5_B SCIA_RX SD1_C1 EQEP1_INDEX PMBUSA_SDA
GPIO18_X2 SPIA_CLK SCIB_TX CANA_RX EPWM6_A I2CA_SCL SD1_D2 EQEP2_A PMBUSA_CTL XCLKOUT
GPIO20
GPIO21
GPIO22_VFBSW EQEP1_STROBE SCIB_TX SPIB_CLK SD1_D4 LINA_TX
GPIO23_VSW
GPIO24 OUTPUTXBAR1 EQEP2_A EPWM8_A SPIB_SIMO SD1_D1 PMBUSA_SCL SCIA_TX ERRORSTS
GPIO25 OUTPUTXBAR2 EQEP2_B SPIB_SOMI SD1_C1 FSITXA_D1 PMBUSA_SDA SCIA_RX
GPIO26 OUTPUTXBAR3 EQEP2_INDEX OUTPUTXBAR3 SPIB_CLK SD1_D2 FSITXA_D0 PMBUSA_CTL I2CA_SDA
GPIO27 OUTPUTXBAR4 EQEP2_STROBE OUTPUTXBAR4 SPIB_STE SD1_C2 FSITXA_CLK PMBUSA_ALERT I2CA_SCL
GPIO28 SCIA_RX EPWM7_A OUTPUTXBAR5 EQEP1_A SD1_D3 EQEP2_STROBE LINA_TX SPIB_CLK ERRORSTS
GPIO29 SCIA_TX EPWM7_B OUTPUTXBAR6 EQEP1_B SD1_C3 EQEP2_INDEX LINA_RX SPIB_STE ERRORSTS
GPIO30 CANA_RX SPIB_SIMO OUTPUTXBAR7 EQEP1_STROBE SD1_D4
GPIO31 CANA_TX SPIB_SOMI OUTPUTXBAR8 EQEP1_INDEX SD1_C4 FSIRXA_D1
GPIO32 I2CA_SDA SPIB_CLK EPWM8_B LINA_TX SD1_D3 FSIRXA_D0 CANA_TX
GPIO33 I2CA_SCL SPIB_STE OUTPUTXBAR4 LINA_RX SD1_C3 FSIRXA_CLK CANA_RX
GPIO34 OUTPUTXBAR1 PMBUSA_SDA
GPIO35 SCIA_RX I2CA_SDA CANA_RX PMBUSA_SCL LINA_RX EQEP1_A PMBUSA_CTL TDI
GPIO37 OUTPUTXBAR2 I2CA_SCL SCIA_TX CANA_TX LINA_TX EQEP1_B PMBUSA_ALERT TDO
GPIO39 CANB_RX FSIRXA_CLK
GPIO40 PMBUSA_SDA FSIRXA_D0 SCIB_TX EQEP1_A
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56 SPIA_CLK EQEP2_STROBE SCIB_TX SD1_D3 SPIB_SIMO EQEP1_A
GPIO57 SPIA_STE EQEP2_INDEX SCIB_RX SD1_C3 SPIB_SOMI EQEP1_B
GPIO58 OUTPUTXBAR1 SPIB_CLK SD1_D4 LINA_TX CANB_TX EQEP1_STROBE
GPIO59 OUTPUTXBAR2 SPIB_STE SD1_C4 LINA_RX CANB_RX EQEP1_INDEX

Table 4-7 lists all muxed signals available and the respective GPIO within each package.

Table 4-7 Digital Signals by GPIO

SIGNAL NAME PIN TYPE DESCRIPTION 100 PZ 64 PMQ 64 PM 56 RSH
ADCSOCAO O ADC Start of Conversion A Output for External ADC (from ePWM modules) GPIO8 GPIO8 GPIO8 GPIO8
ADCSOCBO O ADC Start of Conversion B Output for External ADC (from ePWM modules) GPIO10 GPIO10 GPIO10
CANA_RX I CAN-A Receive GPIO5
GPIO18_X2
GPIO30
GPIO33
GPIO35/TDI		 GPIO5
GPIO18_X2
GPIO33
GPIO35/TDI		 GPIO5
GPIO18_X2
GPIO33
GPIO35/TDI		 GPIO5
GPIO18_X2
GPIO33
GPIO35/TDI
CANA_TX O CAN-A Transmit GPIO4
GPIO31
GPIO32
GPIO37/TDO		 GPIO4
GPIO32
GPIO37/TDO		 GPIO4
GPIO32
GPIO37/TDO		 GPIO4
GPIO32
GPIO37/TDO
CANB_RX I CAN-B Receive GPIO7
GPIO10
GPIO13
GPIO17
GPIO39
GPIO59		 GPIO7
GPIO10
GPIO17		 GPIO7
GPIO10
GPIO13
GPIO17		 GPIO7
GPIO13
GPIO17
CANB_TX O CAN-B Transmit GPIO6
GPIO8
GPIO12
GPIO16
GPIO58		 GPIO6
GPIO8
GPIO16		 GPIO6
GPIO8
GPIO12
GPIO16		 GPIO6
GPIO8
GPIO12
GPIO16
EPWM1_A O ePWM-1 Output A GPIO0 GPIO0 GPIO0 GPIO0
EPWM1_B O ePWM-1 Output B GPIO1 GPIO1 GPIO1 GPIO1
EPWM2_A O ePWM-2 Output A GPIO2 GPIO2 GPIO2 GPIO2
EPWM2_B O ePWM-2 Output B GPIO3 GPIO3 GPIO3 GPIO3
EPWM3_A O ePWM-3 Output A GPIO4 GPIO4 GPIO4 GPIO4
EPWM3_B O ePWM-3 Output B GPIO5 GPIO5 GPIO5 GPIO5
EPWM4_A O ePWM-4 Output A GPIO6 GPIO6 GPIO6 GPIO6
EPWM4_B O ePWM-4 Output B GPIO7 GPIO7 GPIO7 GPIO7
EPWM5_A O ePWM-5 Output A GPIO8
GPIO16		 GPIO8
GPIO16		 GPIO8
GPIO16		 GPIO8
GPIO16
EPWM5_B O ePWM-5 Output B GPIO9
GPIO17		 GPIO9
GPIO17		 GPIO9
GPIO17		 GPIO9
GPIO17
EPWM6_A O ePWM-6 Output A GPIO10
GPIO18_X2		 GPIO10
GPIO18_X2		 GPIO10
GPIO18_X2		 GPIO18_X2
EPWM6_B O ePWM-6 Output B GPIO11 GPIO11 GPIO11 GPIO11
EPWM7_A O ePWM-7 Output A GPIO12
GPIO28		 GPIO28 GPIO12
GPIO28		 GPIO12
GPIO28
EPWM7_B O ePWM-7 Output B GPIO13
GPIO29		 GPIO29 GPIO13
GPIO29		 GPIO13
GPIO29
EPWM8_A O ePWM-8 Output A GPIO14
GPIO24		 GPIO24 GPIO24 GPIO24
EPWM8_B O ePWM-8 Output B GPIO15
GPIO32		 GPIO32 GPIO32 GPIO32
EQEP1_A I eQEP-1 Input A GPIO6
GPIO10
GPIO28
GPIO35/TDI
GPIO40
GPIO56		 GPIO6
GPIO10
GPIO28
GPIO35/TDI		 GPIO6
GPIO10
GPIO28
GPIO35/TDI		 GPIO6
GPIO28
GPIO35/TDI
EQEP1_B I eQEP-1 Input B GPIO7
GPIO11
GPIO29
GPIO37/TDO
GPIO57		 GPIO7
GPIO11
GPIO29
GPIO37/TDO		 GPIO7
GPIO11
GPIO29
GPIO37/TDO		 GPIO7
GPIO11
GPIO29
GPIO37/TDO
EQEP1_INDEX I/O eQEP-1 Index GPIO9
GPIO13
GPIO17
GPIO31
GPIO59		 GPIO9
GPIO17		 GPIO9
GPIO13
GPIO17		 GPIO9
GPIO13
GPIO17
EQEP1_STROBE I/O eQEP-1 Strobe GPIO8
GPIO12
GPIO16
GPIO22_VFBSW
GPIO30
GPIO58		 GPIO8
GPIO16
GPIO22_VFBSW		 GPIO8
GPIO12
GPIO16
GPIO22_VFBSW		 GPIO8
GPIO12
GPIO16
GPIO22_VFBSW
EQEP2_A I eQEP-2 Input A GPIO14
GPIO18_X2
GPIO24		 GPIO18_X2
GPIO24		 GPIO18_X2
GPIO24		 GPIO18_X2
GPIO24
EQEP2_B I eQEP-2 Input B GPIO15
GPIO25
EQEP2_INDEX I/O eQEP-2 Index GPIO26
GPIO29
GPIO57		 GPIO29 GPIO29 GPIO29
EQEP2_STROBE I/O eQEP-2 Strobe GPIO27
GPIO28
GPIO56		 GPIO28 GPIO28 GPIO28
ERRORSTS O Error Status Output. This signal requires an external pullup. GPIO24
GPIO28
GPIO29		 GPIO24
GPIO28
GPIO29		 GPIO24
GPIO28
GPIO29		 GPIO24
GPIO28
GPIO29
FSIRXA_CLK I FSIRX-A Input Clock GPIO4
GPIO13
GPIO33
GPIO39		 GPIO4
GPIO33		 GPIO4
GPIO13
GPIO33		 GPIO4
GPIO13
GPIO33
FSIRXA_D0 I FSIRX-A Primary Data Input GPIO3
GPIO12
GPIO32
GPIO40		 GPIO3
GPIO32		 GPIO3
GPIO12
GPIO32		 GPIO3
GPIO12
GPIO32
FSIRXA_D1 I FSIRX-A Optional Additional Data Input GPIO2
GPIO11
GPIO31		 GPIO2
GPIO11		 GPIO2
GPIO11		 GPIO2
GPIO11
FSITXA_CLK O FSITX-A Output Clock GPIO7
GPIO10
GPIO27		 GPIO7
GPIO10		 GPIO7
GPIO10		 GPIO7
FSITXA_D0 O FSITX-A Primary Data Output GPIO6
GPIO9
GPIO26		 GPIO6
GPIO9		 GPIO6
GPIO9		 GPIO6
GPIO9
FSITXA_D1 O FSITX-A Optional Additional Data Output GPIO5
GPIO8
GPIO25		 GPIO5
GPIO8		 GPIO5
GPIO8		 GPIO5
GPIO8
I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock GPIO1
GPIO8
GPIO18_X2
GPIO27
GPIO33
GPIO37/TDO		 GPIO1
GPIO8
GPIO18_X2
GPIO33
GPIO37/TDO		 GPIO1
GPIO8
GPIO18_X2
GPIO33
GPIO37/TDO		 GPIO1
GPIO8
GPIO18_X2
GPIO33
GPIO37/TDO
I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data GPIO0
GPIO10
GPIO26
GPIO32
GPIO35/TDI		 GPIO0
GPIO10
GPIO32
GPIO35/TDI		 GPIO0
GPIO10
GPIO32
GPIO35/TDI		 GPIO0
GPIO32
GPIO35/TDI
LINA_RX I LIN-A Receive GPIO29
GPIO33
GPIO35/TDI
GPIO59		 GPIO29
GPIO33
GPIO35/TDI		 GPIO29
GPIO33
GPIO35/TDI		 GPIO29
GPIO33
GPIO35/TDI
LINA_TX O LIN-A Transmit GPIO22_VFBSW
GPIO28
GPIO32
GPIO37/TDO
GPIO58		 GPIO22_VFBSW
GPIO28
GPIO32
GPIO37/TDO		 GPIO22_VFBSW
GPIO28
GPIO32
GPIO37/TDO		 GPIO22_VFBSW
GPIO28
GPIO32
GPIO37/TDO
OUTPUTXBAR1 O Output X-BAR Output 1 GPIO2
GPIO24
GPIO34
GPIO58		 GPIO2
GPIO24		 GPIO2
GPIO24		 GPIO2
GPIO24
OUTPUTXBAR2 O Output X-BAR Output 2 GPIO3
GPIO25
GPIO37/TDO
GPIO59		 GPIO3
GPIO37/TDO		 GPIO3
GPIO37/TDO		 GPIO3
GPIO37/TDO
OUTPUTXBAR3 O Output X-BAR Output 3 GPIO4
GPIO5
GPIO14
GPIO26		 GPIO4
GPIO5		 GPIO4
GPIO5		 GPIO4
GPIO5
OUTPUTXBAR4 O Output X-BAR Output 4 GPIO6
GPIO15
GPIO27
GPIO33		 GPIO6
GPIO33		 GPIO6
GPIO33		 GPIO6
GPIO33
OUTPUTXBAR5 O Output X-BAR Output 5 GPIO7
GPIO28		 GPIO7
GPIO28		 GPIO7
GPIO28		 GPIO7
GPIO28
OUTPUTXBAR6 O Output X-BAR Output 6 GPIO9
GPIO29		 GPIO9
GPIO29		 GPIO9
GPIO29		 GPIO9
GPIO29
OUTPUTXBAR7 O Output X-BAR Output 7 GPIO11
GPIO16
GPIO30		 GPIO11
GPIO16		 GPIO11
GPIO16		 GPIO11
GPIO16
OUTPUTXBAR8 O Output X-BAR Output 8 GPIO17
GPIO31		 GPIO17 GPIO17 GPIO17
PMBUSA_ALERT I/OD PMBus-A Open-Drain Bidirectional Alert Signal GPIO13
GPIO27
GPIO37/TDO		 GPIO37/TDO GPIO13
GPIO37/TDO		 GPIO13
GPIO37/TDO
PMBUSA_CTL I PMBus-A Control Signal GPIO12
GPIO18_X2
GPIO26
GPIO35/TDI		 GPIO18_X2
GPIO35/TDI		 GPIO12
GPIO18_X2
GPIO35/TDI		 GPIO12
GPIO18_X2
GPIO35/TDI
PMBUSA_SCL I/OD PMBus-A Open-Drain Bidirectional Clock GPIO3
GPIO15
GPIO16
GPIO24
GPIO35/TDI		 GPIO3
GPIO16
GPIO24
GPIO35/TDI		 GPIO3
GPIO16
GPIO24
GPIO35/TDI		 GPIO3
GPIO16
GPIO24
GPIO35/TDI
PMBUSA_SDA I/OD PMBus-A Open-Drain Bidirectional Data GPIO2
GPIO14
GPIO17
GPIO25
GPIO34
GPIO40		 GPIO2
GPIO17		 GPIO2
GPIO17		 GPIO2
GPIO17
SCIA_RX I SCI-A Receive Data GPIO3
GPIO9
GPIO17
GPIO25
GPIO28
GPIO35/TDI		 GPIO3
GPIO9
GPIO17
GPIO28
GPIO35/TDI		 GPIO3
GPIO9
GPIO17
GPIO28
GPIO35/TDI		 GPIO3
GPIO9
GPIO17
GPIO28
GPIO35/TDI
SCIA_TX O SCI-A Transmit Data GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/TDO		 GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/TDO		 GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/TDO		 GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/TDO
SCIB_RX I SCI-B Receive Data GPIO11
GPIO13
GPIO15
GPIO57		 GPIO11 GPIO11
GPIO13		 GPIO11
GPIO13
SCIB_TX O SCI-B Transmit Data GPIO9
GPIO10
GPIO12
GPIO14
GPIO18_X2
GPIO22_VFBSW
GPIO40
GPIO56		 GPIO9
GPIO10
GPIO18_X2
GPIO22_VFBSW		 GPIO9
GPIO10
GPIO12
GPIO18_X2
GPIO22_VFBSW		 GPIO9
GPIO12
GPIO18_X2
GPIO22_VFBSW
SD1_C1 I SDFM-1 Channel 1 Clock Input GPIO17
GPIO25		 GPIO17 GPIO17 GPIO17
SD1_C2 I SDFM-1 Channel 2 Clock Input GPIO27
SD1_C3 I SDFM-1 Channel 3 Clock Input GPIO29
GPIO33
GPIO57		 GPIO29
GPIO33		 GPIO29
GPIO33		 GPIO29
GPIO33
SD1_C4 I SDFM-1 Channel 4 Clock Input GPIO31
GPIO59
SD1_D1 I SDFM-1 Channel 1 Data Input GPIO16
GPIO24		 GPIO16
GPIO24		 GPIO16
GPIO24		 GPIO16
GPIO24
SD1_D2 I SDFM-1 Channel 2 Data Input GPIO18_X2
GPIO26		 GPIO18_X2 GPIO18_X2 GPIO18_X2
SD1_D3 I SDFM-1 Channel 3 Data Input GPIO28
GPIO32
GPIO56		 GPIO28
GPIO32		 GPIO28
GPIO32		 GPIO28
GPIO32
SD1_D4 I SDFM-1 Channel 4 Data Input GPIO22_VFBSW
GPIO30
GPIO58		 GPIO22_VFBSW GPIO22_VFBSW GPIO22_VFBSW
SPIA_CLK I/O SPI-A Clock GPIO3
GPIO9
GPIO18_X2
GPIO56		 GPIO3
GPIO9
GPIO18_X2		 GPIO3
GPIO9
GPIO18_X2		 GPIO3
GPIO9
GPIO18_X2
SPIA_SIMO I/O SPI-A Slave In, Master Out (SIMO) GPIO8
GPIO16		 GPIO8
GPIO16		 GPIO8
GPIO16		 GPIO8
GPIO16
SPIA_SOMI I/O SPI-A Slave Out, Master In (SOMI) GPIO10
GPIO17		 GPIO10
GPIO17		 GPIO10
GPIO17		 GPIO17
SPIA_STE I/O SPI-A Slave Transmit Enable (STE) GPIO5
GPIO11
GPIO57		 GPIO5
GPIO11		 GPIO5
GPIO11		 GPIO5
GPIO11
SPIB_CLK I/O SPI-B Clock GPIO14
GPIO22_VFBSW
GPIO26
GPIO28
GPIO32
GPIO58		 GPIO22_VFBSW
GPIO28
GPIO32		 GPIO22_VFBSW
GPIO28
GPIO32		 GPIO22_VFBSW
GPIO28
GPIO32
SPIB_SIMO I/O SPI-B Slave In, Master Out (SIMO) GPIO7
GPIO24
GPIO30
GPIO56		 GPIO7
GPIO24		 GPIO7
GPIO24		 GPIO7
GPIO24
SPIB_SOMI I/O SPI-B Slave Out, Master In (SOMI) GPIO6
GPIO25
GPIO31
GPIO57		 GPIO6 GPIO6 GPIO6
SPIB_STE I/O SPI-B Slave Transmit Enable (STE) GPIO15
GPIO27
GPIO29
GPIO33
GPIO59		 GPIO29
GPIO33		 GPIO29
GPIO33		 GPIO29
GPIO33
SYNCOUT O External ePWM Synchronization Pulse GPIO6 GPIO6 GPIO6 GPIO6
TDI I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input. GPIO35/TDI GPIO35/TDI GPIO35/TDI GPIO35/TDI
TDO O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input. GPIO37/TDO GPIO37/TDO GPIO37/TDO GPIO37/TDO
VFBSW - Internal DC-DC regulator feedback signal. If the internal DC-DC regulator is used, tie this pin to the node where L(VSW) connects to the VDD rail (as close as possible to the device). GPIO22_VFBSW GPIO22_VFBSW GPIO22_VFBSW GPIO22_VFBSW
VSW - Switching output of the internal DC-DC regulator GPIO23_VSW GPIO23_VSW GPIO23_VSW GPIO23_VSW
X2 I/O Crystal oscillator output GPIO18_X2 GPIO18_X2 GPIO18_X2 GPIO18_X2
XCLKOUT O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. GPIO16
GPIO18_X2		 GPIO16
GPIO18_X2		 GPIO16
GPIO18_X2		 GPIO16
GPIO18_X2