JAJSRJ3D December   2012  – October 2023 TPD4E1B06

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ultra Low Leakage Current 0.5 nA (Maximum)
      2. 7.3.2 Transient Protection for 4 I/O Lines
      3. 7.3.3 I/O Capacitance 0.7 pF (Typical)
      4. 7.3.4 Bi-Directional (ESD) Protection Diode Array
      5. 7.3.5 Low ESD Clamping Voltage
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on IO1, IO2, IO3, and IO4 Pins
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 Application Information

TPD4E1B06 is an ESD protection diode array which is typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes through the diode, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered diode holds this voltage, VCLAMP, to a safe level to the protected IC.