JAJSJE1A July   2021  – December 2021 TPS1HC100-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 説明
  4. Revision History
  5. Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Accurate Current Sense
      2. 8.3.2 Programmable Current Limit
        1. 8.3.2.1 Capacitive Charging
      3. 8.3.3 Inductive-Load Switching-Off Clamp
      4. 8.3.4 Full Protections and Diagnostics
        1. 8.3.4.1  Short-Circuit and Overload Protection
        2. 8.3.4.2  Open-Load and Short-to-Battery Detection
        3. 8.3.4.3  Short-to-Battery Detection
        4. 8.3.4.4  Reverse-Polarity and Battery Protection
        5. 8.3.4.5  Latch-Off Mode
        6. 8.3.4.6  Thermal Protection Behavior
        7. 8.3.4.7  UVLO Protection
        8. 8.3.4.8  Loss of GND Protection
        9. 8.3.4.9  Loss of Power Supply Protection
        10. 8.3.4.10 Reverse Current Protection
        11. 8.3.4.11 Protection for MCU I/Os
      5. 8.3.5 Diagnostic Enable Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Dynamically Changing Current Limit
        2. 9.2.2.2 AEC Q100-012 Test Grade A Certification
        3. 9.2.2.3 EMC Transient Disturbances Test
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Without a GND Network
      2. 11.2.2 With a GND Network
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • PWP|14
サーマルパッド・メカニカル・データ
発注情報

Thermal Protection Behavior

The thermal protection behavior can be split up into three categories of events that can happen. Figure 8-16 shows each of these categories.

  1. Relative thermal shutdown: the device is enabled into an overcurrent event. The DIAG_EN pin is high so that diagnostics can be monitored on SNS and FLT (however, DIAG_EN being high is not necessary for all protection features to function). The output current rises up to the IILIM level and the FLT goes low while the SNS goes to VSNSFH. With this large amount of current going through the junction temperature of the FET increases rapidly with respect to the controller temperature. When the power FET temperature rises TREL amount above the controller junction temperature ΔT = TFET – TCON > TREL, the device shuts down. The faults are continually shown on SNS and FLT and the part waits for the tRETRY timer to expire. When tRETRY timer expires, because the LATCH pin is low and EN is still high, the device comes back on into this IILIM condition.
  2. Absolute thermal shutdown: the device is still enabled in an overcurrent event with DIAG_EN high and LATCH still low. However, in this case the junction temperature rises up and hits an absolute reference temperature, TABS, and then shuts down. The device does not recover until both TJ < TABS – Thys and the tRETRY timer has expired.
  3. Latch-off mode: the device is enabled into an overcurrent event. The DIAG_EN pin is high so that diagnostics can be monitored on SNS and FLT. The output current rises up to the IILIM level and the FLT goes low while the SNS goes to VSNSFH. If the part shuts down due to a thermal fault, either relative thermal shutdown or absolute thermal shutdown, the device does not enable the channel until either the LATCH pin or the EN pin is toggled.
Figure 8-16 Thermal Behavior