JAJSCS0C December   2016  – January 2018 TPS22810


  1. 特長
  2. アプリケーション
  3. 概要
    1.     概略回路図
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical DC Characteristics
    8. 7.8 Typical AC Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 On and Off Control
      2. 9.3.2 Quick Output Discharge (QOD)
        1. QOD when System Power is Removed
        2. Internal QOD Considerations
      3. 9.3.3 EN/UVLO
      4. 9.3.4 Adjustable Rise Time (CT)
      5. 9.3.5 Thermal Shutdown
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 ON and OFF Control
    3. 10.3 Input Capacitor (Optional)
    4. 10.4 Output Capacitor (Optional)
    5. 10.5 Typical Application
      1. 10.5.1 Design Requirements
      2. 10.5.2 Detailed Design Procedure
        1. Shutdown Sequencing During Unexpected Power Loss
        2. VIN to VOUT Voltage Drop
        3. Inrush Current
      3. 10.5.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報




The TPS22810 is a 6-pin, 2.7-18-V load switch with thermal protection in two separate package options. To reduce voltage drop for low voltage and high current rails, the device implements a low resistance N-channel MOSFET which reduces the drop out voltage across the device.

The device starts its operation by monitoring the VIN bus. When VIN exceeds the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on this pin enables the internal MOSFET. As VIN rises, the internal MOSFET of the device starts conducting and allow current to flow from VIN to VOUT. When EN/UVLO is held low (below VENF), internal MOSFET is turned off.

A voltage V(EN/UVLO) < V(ENF) on this pin turns off the internal FET, thus disconnecting VIN from VOUT, while voltage below V(SHUTF) takes the device into shutdown mode, with IQ less than 1 μA to ensure minimal power loss.

The device has a configurable slew rate which helps reduce or eliminate power supply droop because of large inrush currents. The device also features an internal RPD resistor, which discharges VOUT once the switch is disabled.

During shutdown, the device has very low leakage currents, thereby reducing unnecessary leakages for downstream modules during standby. Integrated control logic, driver, charge pump, and output discharge FET eliminates the need for any external components which reduces solution size and bill of materials (BOM) count.

The device also features a QOD pin, which allows the configuration of the discharge rate of VOUT once the switch is disabled.

The device has a thermal protection feature. Due to this device protects itself against thermal damage due to over-temperature and over-current conditions. Safe Operating Area (SoA) requirements are thus inherently met without any special design consideration by the board designer.