JAJSCB4B July   2016  – December 2019 TPS22918-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      オン抵抗と入力電圧の標準値との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical DC Characteristics
    8. 6.8 Typical AC Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 On and Off Control
      2. 8.3.2 Quick Output Discharge (QOD)
        1. 8.3.2.1 QOD when System Power is Removed
        2. 8.3.2.2 Internal QOD Considerations
      3. 8.3.3 Adjustable Rise Time (CT)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitor (CIN)
        2. 9.2.2.2 Output Capacitor (CL) (Optional)
        3. 9.2.2.3 Shutdown Sequencing During Unexpected System Power Loss
        4. 9.2.2.4 VIN to VOUT Voltage Drop
        5. 9.2.2.5 Inrush Current
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.5 Inrush Current

Use Equation 9 to determine how much inrush current is caused by the CL capacitor.

Equation 9. TPS22918-Q1 Q3_Iinhush_slvsco0.gif

where

  • IINRUSH is the amount of inrush caused by CL
  • CL is the capacitance on VOUT
  • dt is the output voltage rise time during the ramp up of VOUT when the device is enabled
  • dVOUT is the change in VOUT during the ramp up of VOUT when the device is enabled

The appropriate rise time can be calculated using the design requirements and the inrush current equation. As the rise time (measured from 10% to 90% of VOUT) is calculated, this is accounted in the dVOUT parameter (80% of VOUT = 4 V) as shown in Equation 10.

Equation 10. 400 mA = 22 μF × 4 V/dt
Equation 11. dt = 220 μs

To ensure an inrush current of less than 400 mA, choose a CT value that yields a rise time of more than 220 μs. Refering to the Table 2 at VIN = 5 V, CT = 220 μF provides a typical rise time of 650 μs. Adding this rise time and voltage into Equation 9, yields Equation 12.

Equation 12. IInrush = 22 μF × 4 V / 650 μs
Equation 13. IInrush = 135 mA

This inrush current can be seen in the Application Curves section. An appropriate CL value must be placed on VOUT such that the IMAX and IPLS specifications of the device are not violated.