SLVSAL2G January   2011  – November 2015 TPS24710 , TPS24711 , TPS24712 , TPS24713

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DETAILED PIN DESCRIPTIONS
        1. 8.3.1.1  EN
        2. 8.3.1.2  FLT
        3. 8.3.1.3  FLTb
        4. 8.3.1.4  GATE
        5. 8.3.1.5  GND
        6. 8.3.1.6  OUT
        7. 8.3.1.7  PG
        8. 8.3.1.8  PGb
        9. 8.3.1.9  PROG
        10. 8.3.1.10 SENSE
        11. 8.3.1.11 TIMER
        12. 8.3.1.12 VCC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Board Plug In
      2. 8.4.2 Inrush Operation
      3. 8.4.3 Action of the Constant-Power Engine
      4. 8.4.4 Circuit Breaker and Fast Trip
      5. 8.4.5 Automatic Restart
      6. 8.4.6 PG, FLT, PGb, FLTb, and Timer Operations
      7. 8.4.7 Overtemperature Shutdown
      8. 8.4.8 Start-Up of Hot-Swap Circuit by VCC or EN
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power-Limited Start-Up
          1. 9.2.2.1.1 STEP 1. Choose RSENSE
          2. 9.2.2.1.2 STEP 2. Choose MOSFET M1
          3. 9.2.2.1.3 STEP 3. Choose Power-Limit Value, PLIM, and RPROG
          4. 9.2.2.1.4 STEP 4. Choose Output Voltage Rising Time, tON, CT
          5. 9.2.2.1.5 STEP 5. Calculate the Retry-Mode Duty Ratio
          6. 9.2.2.1.6 STEP 6. Select R1 and R2 for UV
          7. 9.2.2.1.7 STEP 7. Choose RGATE, R4, R5 and C1
        2. 9.2.2.2 Additional Design Considerations
          1. 9.2.2.2.1 Use of PG/PGb
          2. 9.2.2.2.2 Output Clamp Diode
          3. 9.2.2.2.3 Gate Clamp Diode
          4. 9.2.2.2.4 High-Gate-Capacitance Applications
          5. 9.2.2.2.5 Bypass Capacitors
          6. 9.2.2.2.6 Output Short-Circuit Measurements
          7. 9.2.2.2.7 Using Soft Start with TPS2471x
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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8 Detailed Description

8.1 Overview

The following description relies on the Typical Application (12 V at 10 A), as well as the functional block diagram in Figure 26.

8.2 Functional Block Diagram

TPS24710 TPS24711 TPS24712 TPS24713 B0438-02_LVSAL2.gif

NOTE:

Pins 1 and 10 are PG and FLT, respectively, for TPS24712/13
Figure 26. Block Diagram of the TPS24710/11

8.3 Feature Description

8.3.1 DETAILED PIN DESCRIPTIONS

8.3.1.1 EN

Applying a voltage of 1.35 V or more to this pin enables the gate driver. The addition of an external resistor divider allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets the TPS24710/11/12/13 that has latched off due to a fault condition. This pin should not be left floating.

8.3.1.2 FLT

FLT is assigned for TPS24712/13. This active-high open-drain output assumes high-impedance when TPS24712/13 has remained in current limit long enough for the fault timer to expire. The behavior of the FLT pin depends on the version of the IC. The TPS24712 operates in latch mode and the TPS24713 operates in retry mode. In latch mode, a fault timeout disables the external MOSFET and holds FLT in open drain condition. The latched mode of operation is reset by cycling EN or VCC. In retry mode, a fault timeout first disables the external MOSFET, next waits sixteen cycles of TIMER charging and discharging, and finally attempts a restart. This process repeats as long as the fault persists. In retry mode, the FLT pin goes open-drain whenever the external MOSFET is disabled by the fault timer. In a sustained fault, the FLT waveform becomes a train of pulses. The FLT pin does not assert if the external MOSFET is disabled by EN, overtemperature shutdown, or UVLO. This pin can be left floating when not used.

8.3.1.3 FLTb

FLTb is assigned for TPS24710/11. This active-low open-drain output pulls low when TPS24710/11/12/13 has remained in current limit long enough for the fault timer to expire. The behavior of the FLTb pin depends on the version of the IC. The TPS24710 operates in latch mode and the TPS24711 operates in retry mode. In latch mode, a fault timeout disables the external MOSFET and holds FLTb low. The latched mode of operation is reset by cycling EN or VCC. In retry mode, a fault timeout first disables the external MOSFET, next waits sixteen cycles of TIMER charging and discharging, and finally attempts a restart. This process repeats as long as the fault persists. In retry mode, the FLTb pin is pulled low whenever the external MOSFET is disabled by the fault timer. In a sustained fault, the FLTb waveform becomes a train of pulses. The FLTb pin does not assert if the external MOSFET is disabled by EN, overtemperature shutdown, or UVLO. This pin can be left floating when not used.

8.3.1.4 GATE

This pin provides gate drive to the external MOSFET. A charge pump sources 30 µA to enhance the external MOSFET. A 13.9-V clamp between GATE and VCC limits the gate-to-source voltage, because VVCC is very close to VOUT in normal operation. During start-up, a transconductance amplifier regulates the gate voltage of M1 to provide inrush current limiting. The TIMER pin charges timer capacitor CT during the inrush. Inrush current limiting continues until the V(GATE – VCC) exceeds the Timer Activation Voltage (5.9 V for VVCC = 12 V). Then the TPS24710/11/12/13 enters into circuit-breaker mode. The Timer Activation Voltage is defined as a threshold voltage. When V(GATE-VCC) exceeds this threshold voltage, the inrush operation is finished and the TIMER stops sourcing current and begins sinking current. In the circuit-breaker mode, the current flowing in RSENSE is compared with the current-limit threshold derived from the MOSFET power-limit scheme (see PROG). If the current flowing in RSENSE exceeds the current limit threshold, then MOSFET M1 is turned off. The GATE pin is disabled by the following three conditions:

  1. GATE is pulled down by an 11-mA current source when
    • The fault timer expires during an overload current fault (VSENSE > 25 mV)
    • VEN is below its falling threshold
    • VVCC drops below the UVLO threshold
  2. GATE is pulled down by a 1 A current source for 13.5 µs when a hard output short circuit occurs and V(VCC – SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the external MOSFET remains off.
  3. GATE is discharged by a 20 kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold.

GATE remains low in latch mode (TPS24710/12) and attempts a restart periodically in retry mode (TPS24711/13).

No external resistor should be directly connected from GATE to GND or from GATE to OUT.

8.3.1.5 GND

This pin is connected to system ground.

8.3.1.6 OUT

This pin allows the controller to measure the drain-to-source voltage across the external MOSFET M1. The power-good indicator (PG/PGb) relies on this information, as does the power limiting engine. The OUT pin should be protected from negative voltage transients by a clamping diode or sufficient capacitors. A Schottky diode of 3 A / 40 V in a SMC package is recommended as a clamping diode for high-power applications. The OUT pin should be bypassed to GND with a low-impedance ceramic capacitor in the range of 10 nF to 1 μF.

8.3.1.7 PG

PG is assigned for TPS24712/13. This active-high, open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PG assumes high-impedance after the drain-to-source voltage of the FET has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It pulls low when VDS exceeds 240 mV. PG assumes low-impedance status after a 3.4-ms deglitch delay once VDS of M1 rises up, resulting from GATE being pulled to GND at any of the following conditions:

  • An overload current fault occurs (VSENSE > 25 mV).
  • A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, i.e., the fast-trip shutdown threshold has been exceeded.
  • VEN is below its falling threshold.
  • VVCC drops below the UVLO threshold.
  • Die temperature exceeds the OTSD threshold.

This pin can be left floating when not used.

8.3.1.8 PGb

PGb is assigned for TPS24710/11. This active-low, open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PGb pulls low after the drain-to-source voltage of the FET has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It goes open-drain when VDS exceeds 240 mV. PGb assumes high-impedance status after a 3.4-ms deglitch delay once VDS of M1 rises up, resulting from GATE being pulled to GND at any of the following conditions:

  • An overload current fault occurs (VSENSE > 25 mV).
  • A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, i.e., the fast-trip shutdown threshold has been exceeded.
  • VEN is below its falling threshold.
  • VVCC drops below the UVLO threshold.
  • Die temperature exceeds the OTSD threshold.

This pin can be left floating when not used.

8.3.1.9 PROG

A resistor from this pin to GND sets the maximum power permitted in the external MOSFET M1 during inrush. Do not apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of 4.99 kΩ. To set the maximum power, use Equation 1.

Equation 1. TPS24710 TPS24711 TPS24712 TPS24713 EQ_rprog_LVSAL2.gif

To compute the Power limit based on an existing RPROG use Equation 2.

Equation 2. TPS24710 TPS24711 TPS24712 TPS24713 EQ_Plim_1_LVSAL2.gif

where PLIM is the allowed power limit of MOSFET M1. RSENSE is the load-current-monitoring resistor connected between the VCC pin and the SENSE pin. RPROG is the resistor connected from the PROG pin to GND. Both RPROG and RSENSE are in ohms and PLIM is in watts. PLIM is determined by the maximum allowed thermal stress of MOSFET M1, given by Equation 3,

Equation 3. TPS24710 TPS24711 TPS24712 TPS24713 EQ_Plim_2_LVSAL1.gif

where TJ(MAX) is the maximum desired transient junction temperature and TC(MAX) is the maximum case temperature prior to a start or restart. RӨJC(MAX) is the junction-to-case thermal impedance of the pass MOSFET M1 in units of °C/W. Both TJ(MAX) and TC(MAX) are in °C.

8.3.1.10 SENSE

This pin connects to the negative terminal of RSENSE. It provides a means of sensing the voltage across this resistor, as well as a way to monitor the drain-to-source voltage across the external FET. The current limit ILIM is set by Equation 4.

Equation 4. TPS24710 TPS24711 TPS24712 TPS24713 EQ_Ilim_LVSAL2.gif

A fast trip shutdown occurs when V(VCC – VSENSE) exceeds 60 mV.

8.3.1.11 TIMER

A capacitor CT connected from the TIMER pin to GND determines the overload fault timing. TIMER sources 10 µA when an overload is present, and discharges CT at 10 µA otherwise. M1 is turned off when VTIMER reaches 1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period before the external MOSFET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure proper operation of the fault timer. The value of CT can be calculated from the desired fault time tFLT, using Equation 5.

Equation 5. TPS24710 TPS24711 TPS24712 TPS24713 EQ_Ct_1_LVSAL1.gif

The latch mode (TPS24710/12) or the retry mode (TPS24711/13) occurs if the load current exceeds the current limit threshold or the fast-trip shutdown threshold, While in latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically. In retry mode, the external MOSFET is disabled for sixteen cycles of TIMER charging and discharging. The TIMER pin is pulled to GND by a 2-mA current source at the end of the 16th cycle of charging and discharging. The external MOSFET is then re-enabled. The TIMER pin capacitor, CT, can also be discharged to GND during latch mode or retry mode by a 2-mA current source whenever any of the following occurs:

  • VEN is below its falling threshold.
  • VVCC drops below the UVLO threshold.

8.3.1.12 VCC

This pin performs three functions. First, it provides biasing power to the integrated circuit. Second, it serves as an input to the power-on reset (POR) and undervoltage lockout (UVLO) functions. The VCC trace from the integrated circuit should connect directly to the positive terminal of RSENSE to minimize the voltage sensing error. Bypass capacitor C1, shown in the typical application diagram on the front page, should be connected to the positive terminal of RSENSE. A capacitance of at least 10 nF is recommended.

8.4 Device Functional Modes

The TPS24710/11/12/13 provides all the features needed for a positive hot-swap controller. These features include:

  • Undervoltage lockout
  • Adjustable (system-level) enable
  • turn-on inrush limiting
  • High-side gate drive for an external N-channel MOSFET
  • MOSFET protection by power limiting
  • Adjustable overload timeout — also called an electronic circuit breaker
  • Charge-complete indicator for downstream converter coordination
  • A choice of latch (TPS24710/12) or automatic restart mode (TPS24711/13)

The Typical Application (12 V at 10 A), and oscilloscope plots shown in Figure 27 through Figure 29 and Figure 31 through Figure 34, demonstrate many of the functions described previously.

8.4.1 Board Plug In

Figure 27 and Figure 28 illustrate the inrush current that flows when a hot swap board under the control of the TPS24710/11/12/13 is plugged into a system bus. Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in. The TPS24710/11/12/13 is held inactive, for a short period while internal voltages stabilize. During this period GATE, PROG, TIMER are held low and PG, FLT, PGb, and FLTb are held open drain. When the voltage on the internal VCC rail exceeds approximately 1.5 V, the power-on reset (POR) circuit initializes the TPS24710/11/12/13 and a start-up cycle is ready to take place.

GATE, PROG, TIMER, PG, FLT, PGb, and FLTb are released after the internal voltages have stabilized and the external EN (enable) thresholds have been exceeded. The part begins sourcing current from the GATE pin to turn on MOSFET M1. The TPS24710/11/12/13 monitors both the drain-to-source voltage across MOSFET M1 and the drain current passing through it. Based on these measurements, the TPS24710/11/12/13 limits the drain current by controlling the gate voltage so that the power dissipation within the MOSFET does not exceed the power limit programmed by the user. The current increases as the voltage across the MOSFET decreases until finally the current reaches the current limit ILIM.

TPS24710 TPS24711 TPS24712 TPS24713 C001_LVSAL2.gif Figure 27. Inrush Mode at Hot-Swap Circuit Insertion

8.4.2 Inrush Operation

After TPS24710/11/12/13 initialization is complete (as described in the Board Plug-In section) and EN is active, GATE is enabled (VGATE starts increasing). When VGATE reaches the MOSFET M1 gate threshold, a current flows into the downstream bulk storage capacitors. When this current exceeds the limit set by the power limit engine, the gate of the MOSFET is regulated by a feedback loop to make the MOSFET current rise in a controlled manner. This not only limits the inrush current charging capacitance but it also limits the power dissipation of the MOSFET to safe levels. A more complete explanation of the power limiting scheme is given in the section entitled Action of the Constant Power Engine. When Gate is enabled, the TIMER pin begins to charge the timing capacitor CT with a current of approximately 10 μA. The TIMER pin continues to charge CT until V(GATE – VCC) reaches the timer activation voltage (5.9 V for VVCC = 12 V). The TIMER then begins to discharge CT with a current of approximately 10 μA. This indicates that the inrush mode is finished. If the TIMER exceeds its upper threshold of 1.35 V before V(GATE – VCC) reaches the timer activation voltage, the GATE pin is pulled to GND and the hot-swap circuit enters either latch mode (TPS24710/12) or auto-retry mode (TPS24711/13).

The power limit feature is disabled once the inrush operation is finished and the hotswap circuit becomes a circuit breaker. The TPS24710/11/12/13 will turn off the MOSFET, M1, after a fault timer period once the load exceeds the current limit threshold.

8.4.3 Action of the Constant-Power Engine

Figure 28 illustrates the operation of the constant-power engine during start-up. The circuit used to generate the waveforms of Figure 28 was programmed to a power limit of 29.3 W by means of the resistor connected between PROG and GND. At the moment current begins to flow through the MOSFET, a voltage of 12 V appears across it (input voltage VVCC = 12 V), and the constant-power engine therefore allows a current of 2.44 A (equal to 29.3 W divided by 12 V) to flow. This current increases in inverse ratio as the drain-to-source voltage diminishes, so as to maintain a constant dissipation of 29.3 W. The constant-power engine adjusts the current by altering the reference signal fed to the current limit amplifier. The lower part of Figure 29 shows the measured power dissipated within the MOSFET, labeled FET PWR, remaining substantially constant during this period of operation, which ends when the current through the MOSFET reaches the current limit ILIM. This behavior can be considered a form of foldback limiting, but unlike the standard linear form of foldback limiting, it allows the power device to operate near its maximum capability, thus reducing the start-up time and minimizing the size of the required MOSFET.

TPS24710 TPS24711 TPS24712 TPS24713 C002_LVSAL1.gif Figure 28. Computation of M1 Power Stress During Start-Up

8.4.4 Circuit Breaker and Fast Trip

The TPS24710/11/12/13 monitors load current by sensing the voltage across RSENSE. The TPS24710/11/12/13 incorporates two distinct thresholds: a current-limit threshold and a fast-trip threshold.

The functions of circuit breaker and fast-trip turn off are shown in Figure 29 through Figure 32.

Figure 29 shows the behavior of the TPS24710/11 when a fault in the output load causes the current passing through RSENSE to increase to a value above the current limit but less than the fast-trip threshold. When the current exceeds the current-limit threshold, a current of approximately 10 μA begins to charge timing capacitor CT. If the voltage on CT reaches 1.35 V, then the external MOSFET is turned off. The TPS24710 latches off and the TPS24711 commences a restart cycle. In either event, fault pin FLTb pulls low to signal a fault condition. Overload between the current limit and the fast trip threshold is permitted for this period. This shutdown scheme is sometimes called an electronic circuit breaker.

The fast-trip threshold protects the system against a severe overload or a dead short circuit. When the voltage across the sense resistor RSENSE exceeds the 60 mV fast-trip threshold, the GATE pin immediately pulls the external MOSFET gate to ground with approximately 1 A of current. This extremely rapid shutdown may generate disruptive transients in the system, in which case a low-value resistor inserted between the GATE pin and the MOSFET gate can be used to moderate the turn off current. The fast-trip circuit holds the MOSFET off for only a few microseconds, after which the TPS24710/11/12/13 turns back on slowly, allowing the current-limit feedback loop to take over the gate control of M1. Then the hot-swap circuit goes into either latch mode (TPS24710/12) or auto-retry mode (TPS24711/13). Figure 31 and Figure 32 illustrate the behavior of the system implementing TPS24710/11 when the current exceeds the fast-trip threshold.

TPS24710 TPS24711 TPS24712 TPS24713 C003_LVSAL1.gif Figure 29. Circuit Breaker Mode During Over Load Condition
TPS24710 TPS24711 TPS24712 TPS24713 B0439-02_LVSAL2.gif Figure 30. Partial Diagram of the TPS24710/11/12/13 With Selected External Components
TPS24710 TPS24711 TPS24712 TPS24713 C004_LVSAL1.gif Figure 31. Current Limit During Output Load Short Circuit Condition (Overview)
TPS24710 TPS24711 TPS24712 TPS24713 C005_LVSAL1.gif Figure 32. Current Limit During Output-Load Short-Circuit Condition (Onset)

8.4.5 Automatic Restart

The TPS24711/13 automatically initiates a restart after a fault has caused it to turn off the external MOSFET M1. Internal control circuits use CT to count 16 cycles before re-enabling M1 as shown in Figure 33 (TPS24711). This sequence repeats if the fault persists. The timer has a 1 : 1 charge-to-discharge current ratio. For the very first cycle, the TIMER pin starts from 0 V and rises to the upper threshold of 1.35 V and subsequently falls to 0.35 V before restarting. For the following 16 cycles, 0.35 V is used as the lower threshold. This small duty cycle often reduces the average short-circuit power dissipation to levels associated with normal operation and eliminates special thermal considerations for surviving a prolonged output short.

TPS24710 TPS24711 TPS24712 TPS24713 C006_LVSAL1.gif Figure 33. Auto-Restart Cycle Timing
TPS24710 TPS24711 TPS24712 TPS24713 C007_LVSAL1.gif Figure 34. Latch After Overload Fault

8.4.6 PG, FLT, PGb, FLTb, and Timer Operations

The open-drain PG/PGb (PG is for TPS24712/13 and PGb is for TPS24710/11) output provides a deglitched end-of-inrush indication based on the voltage across M1. PG/PGb is useful for preventing a downstream dc/dc converter from starting while its input capacitor COUT is still charging. PG goes active-high and PGb goes active-low about 3.4 ms after COUT is charged. This delay allows M1 to fully turn on and any transients in the power circuits to end before the converter starts up. This type of sequencing prevents the downstream converter from demanding full current before the power-limiting engine allows the MOSFET to conduct the full current set by the current limit ILIM. Failure to observe this precaution may prevent the system from starting. The pullup resistor shown on the PG/PGb pin in the typical application diagram on the front page is illustrative only; the actual connection to the converter depends on the application. The PG/PGb pin may indicate that inrush has ended before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its full operating voltage. Care should be taken to ensure that the MOSFET on-resistance is sufficiently small to ensure that the voltage drop across this transistor is less than the minimum power-good threshold of 140 mV. After the hot-swap circuit successfully starts up, the PG pin can return to a low-impedance status and PGb to high-impedance status whenever the drain-to-source voltage of MOSFET M1 exceeds its upper threshold of 340 mV, which presents the downstream converters a warning flag. This flag may occur as a result of overload fault, output short fault, input overvoltage, higher die temperature, or the GATE shutdown by UVLO and EN.

FLT/FLTb (FLT is for TPS24712/13 and FLTb is for TPS24710/11) is an indicator that the allowed fault-timer period during which the load current can exceed the programmed current limit (but not the fast-trip threshold) has expired. The fault timer starts when a current of approximately 10 μA begins to flow into the external capacitor, CT, and ends when the voltage of CT reaches TIMER upper threshold, i.e., 1.35 V. FLT goes high and FLTb pulls low at the end of the fault timer. Otherwise, FLT assumes a low-impedance state and FLTb a high-impedance state.

The fault-timer state requires an external capacitor CT connected between the TIMER pin and GND pin. The length of the fault timer is the charging time of CT from 0 V to its upper threshold of 1.35 V. The fault timer begins to count under any of the following three conditions:

  1. In the inrush mode, TIMER begins to source current to the timer capacitor, CT, when MOSFET M1 is enabled. TIMER begins to sink current from the timer capacitor, CT when V(GATE – VCC) exceeds the timer activation voltage (see the Inrush Operation section). If V(GATE – VCC) does not reach the timer activation voltage before TIMER reaches 1.35 V, then the TPS24710/11/12/13 disables the external MOSFET M1. After the MOSFET turns off, the timer goes into either latch mode (TPS24710/12) or retry mode (TPS24711/13).
  2. In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24710/12) or retry mode (TPS24711/13).
  3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, CT, when the load current exceeds the programmed current limits following a fast-trip shutdown of M1. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24710/12) or retry mode (TPS24711/13).

If the fault current drops below the programmed current limit within the fault timer period, VTIMER decreases and the pass MOSFET remains enabled.

The behaviors of TIMER are different in the latch mode (TPS24710/12) and retry mode (TPS24711/13). If the timer capacitor reaches the upper threshold of 1.35 V, then:

  • In latch mode, the GATE remains low and the TIMER pin continues to charge and discharge the attached capacitor periodically until TPS24710/12 is disabled by UVLO or EN as shown in Figure 34.
  • In retry mode, TIMER charges and discharges CT between the lower threshold of 0.35 V and the upper threshold of 1.35 V for sixteen cycles before the TPS24711/13 attempts to re-start. The TIMER pin is pulled to GND at the end of the 16th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is removed or the TPS24711/13 is disabled by UVLO or EN.

8.4.7 Overtemperature Shutdown

The TPS24710/11/12/13 includes a built-in overtemperature shutdown circuit designed to disable the gate driver if the die temperature exceeds approximately 140°C. An overtemperature condition also causes the FLT, PG, FLTb and PGb pins to go to high-impedance states. Normal operation resumes once the die temperature has fallen approximately 10°C.

8.4.8 Start-Up of Hot-Swap Circuit by VCC or EN

The connection and disconnection between a load and the system bus are controlled by turning on and turning off the MOSFET, M1.

The TPS24710/11/12/13 has two ways to turn on MOSFET M1:

  1. Increasing VVCC above UVLO upper threshold while EN is already higher than its upper threshold sources current to the GATE pin. After an inrush period, TPS24710/11/12/13 fully turns on MOSFET M1.
  2. Increasing EN above its upper threshold while VVCC is already higher than UVLO upper threshold sources current to the GATE pin. After an inrush period, TPS24710/11/12/13 fully turns on MOSFET M1.

The EN pin can be used to start up the TPS24710/11/12/13 at a selected input voltage VVCC.

To isolate the load from the system bus, the GATE pin sinks current and pulls the gate of MOSFET M1 low. The MOSFET can be disabled by any of the following conditions: UVLO, EN, load current above current limit threshold, hard short at load, or OTSD. Three separate conditions pull down the GATE pin:

  1. GATE is pulled down by an 11-mA current source when any of the following occurs.
    • The fault timer expires during an overload current fault (VSENSE > 25 mV).
    • VEN is below its falling threshold.
    • VVCC drops below the UVLO threshold.
  2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V(VCC – SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the external MOSFET remains off.
  3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold.