SLVSA75A July   2010  – August 2015 TPS386596

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Monitoring
      2. 8.3.2 Manual Reset
      3. 8.3.3 Reset Output
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Undervoltage Detection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Spice Models
      2. 12.1.2 Device Nomenclature
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted).(1)(2)
MIN MAX UNIT
Voltage Input, VDD –0.3 7 V
VMR, VSENSE1, VSENSE2, VSENSE3, VSENSE4, VRESET –0.3 7 V
Current RESET pin 5 mA
Power dissipation Continuous total See Thermal Information
Temperature Operating virtual junction, TJ –40 150 °C
Operating ambient, TA –40 125
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted).
MIN NOM MAX UNIT
VDD 1.8 6.5 V
VSENSE(1) 0 VDD V
VMR 0 VDD V
VRESET 0 6.5 V
RPULL-UP 6.5 100 10,000
TJ –40 25 125 °C
(1) All sense inputs.

6.4 Thermal Information

THERMAL METRIC(1) TPS386596 UNIT
DGK (VSSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance 174 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.5 °C/W
RθJB Junction-to-board thermal resistance 94 °C/W
ψJT Junction-to-top characterization parameter 1.9 °C/W
ψJB Junction-to-board characterization parameter 92.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over the operating temperature range of TJ = –40°C to 125°C. 1.8 V < VDD < 6.5 V, RRESET = 100 kΩ to VDD, CRESET = 50 pF to GND, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Input supply 1.8 6.5 V
IDD Supply current (current into VDD pin) VCC = 3.3 V, RESET not asserted 7 19 µA
VCC = 6.5 V, RESET not asserted 7.5 22 µA
Power-on reset voltage(1)(2) VOL(max) = 0.2 V, IRESET = 15 µA 0.9 V
VITn Negative-going input threshold accuracy SENSE1 2.87 2.90 2.93 V
SENSE2, SENSE3, SENSE4 396 400 404 mV
VHYS Hysteresis (positive-going) on VITn SENSE1 25 72 mV
SENSE2, SENSE3, SENSE4 3.5 10 mV
ISENSE1 Input current at SENSE1 VSENSE1 = 3.3 V 2.2 2.75 3.3 µA
ISENSEn Input current at SENSEn pin,
n = 2, 3, 4
VSENSEn = 0.42 V –25 25 nA
td RESETdelay time 30 50 70 ms
VIL MR logic low input 0 0.3VDD V
VIH MR logic high input 0.7VDD V
RMR_Pullup Internal pullup resistor on MR pin to VDD 100
VOL Low-level RESET output voltage IOL = 1 mA 0.4 V
SENSEn = 0 V, 1.3 V < VDD < 1.8 V,
IOL = 0.4 mA(1)
0.3
ILKG RESET leakage current VRESET = 6.5 V, RESET not asserted –300 300 nA
CIN Input pin capacitance 5 pF
(1) These specifications are out of recommended VDD range and only define RESET output performance during VDD ramp up.
(2) The lowest supply voltage (VDD) at which RESET becomes active. tRISE(VDD) ≥ 15 µs/V.

6.6 Timing Requirements

Over the operating temperature range of TJ = –40°C to 125°C. 1.8 V < VDD < 6.5 V, RRESET = 100 kΩ to VDD, CRESET = 50 pF to GND, unless otherwise noted. Typical values are at TJ = 25°C.
MIN NOM MAX UNIT
tW Input pulse width to SENSEn and MR pins SENSEm: 1.05 VIT ≥ 0.95 VIT 4 μs
MR: 0.7 VDD ≥ 0.3 VDD 50 ns

6.7 Switching Characteristics

Over the operating temperature range of TJ = –40°C to 125°C. 1.8 V < VDD < 6.5 V, RRESET = 100 kΩ to VDD, CRESET = 50 pF to GND, unless otherwise noted. Typical values are at TJ = 25°C.
MIN TYP MAX UNIT
tD RESET delay time 30 50 70 ms
TPS386596 TimeDgm_lvsa75.gifFigure 1. Timing Diagram

6.8 Typical Characteristics

At TA = 25°C, and VDD = 3.3 V, unless otherwise noted.
TPS386596 D001_SLVSA75.gif
Figure 2. Supply Current vs Supply Voltage
TPS386596 D003_SLVSA75.gif
Figure 4. SENSEn Minimum Pulse Width vs SENSEn Threshold Overdrive Voltage
TPS386596 D005_SLVSA75.gif
Figure 6. SENSE2 Threshold and Hysteresis vs Temperature
TPS386596 D007_SLVSA75.gif
Figure 8. SENSE4 Threshold and Hysteresis vs Temperature
TPS386596 D009_SLVSA75.gif
Figure 10. Output Voltage Low at 1 mA vs Temperature
TPS386596 D011_SLVSA75.gif
Figure 12. MR Minimum Pulse Width vs MR Threshold Overdrive Voltage
TPS386596 D002_SLVSA75.gif
Figure 3. Reset Delay vs Temperature
TPS386596 D004_SLVSA75.gif
Figure 5. SENSE1 Threshold and Hysteresis vs Temperature
TPS386596 D006_SLVSA75.gif
Figure 7. SENSE3 Threshold and Hysteresis vs Temperature
TPS386596 D008_SLVSA75.gif
Figure 9. Output Voltage Low vs Output Current
TPS386596 D010_SLVSA75.gif
Figure 11. MR Threshold vs Temperature