JAJSQQ7 july   2023 TPS38700S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Sync Functionality
      3. 8.3.3 Transitioning Sequences
        1. 8.3.3.1 Power Up
        2. 8.3.3.2 Power Down
        3. 8.3.3.3 Emergency Power Down
      4. 8.3.4 BACKUP State
      5. 8.3.5 Thermal Shutdown (TSD) State
      6. 8.3.6 I2C
        1. 8.3.6.1 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Test Implementation
      5. 9.2.5 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.6 I2C

TPS38700S-Q1 follows the I2C protocol (up to 1MHz) to manage communication with host devices such as a MCU or System on Chip (SoC). I2C is a two wire communication protocol implmented using two signals, clock (SCL) and data (SDA). The host device is the primary controller of communication. TPS38700S-Q1 responds over the data line during read or write operations as defined by I2C protocol. Both SCL and SDA signals are open drain topology and can be used in a wired-OR configuration with other devices to share the communication bus. Both SCL and SDA pins need an external pull up resistor to supply voltage (10 kΩ recommended).

Figure 8-7 shows the timing relationship between SCL and SDA lines to transfer 1 byte of data. SCL line is always controlled by host. To transfer 1 byte data, host needs to send 9 clocks on SCL. 8 clocks for data and 1 clock for ACK or NACK. SDA line is controlled by either the host or TPS38700S-Q1 based on the read or write operation. Figure 8-8 and Figure 8-9 highlight the communication protocol flow and which device controls SDA line at various instances during active communication.

GUID-20230413-SS0I-ZDNW-G9RJ-WDWHBSC0RJ3M-low.svgFigure 8-7 SCL to SDA Timing for 1 Byte Data Transfer
GUID-20230531-SS0I-G0ZL-GVTN-RHGRLFFVJG4B-low.svgFigure 8-8 I2C Write Protocol
GUID-20230531-SS0I-CCMH-JRZL-3ZZKK0FPWJHF-low.svgFigure 8-9 I2C Read Protocol

Before initiating communication over I2C protocol, host needs to confirm the I2C bus is available for communication. Monitor the SCL and SDA lines, if any line is pulled low, the I2C bus is occupied. Host needs to wait until the bus is available for communication. Once the bus is available for communication, the host can initiate read or write operation by issuing a START condition. Once the I2C communication is complete, release the bus by issuing STOP command. Figure 8-10 shows how to implement START and STOP condition.

GUID-20230413-SS0I-STGZ-DVZN-KNPLXXNN30CZ-low.svgFigure 8-10 I2C START and STOP Condition