SLUS930D Data sheet

SLUS930D April 2011 – November 2016 TPS40400

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RHL|24
- MPQF163I

サーマルパッド・メカニカル・データ

発注情報

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
Input voltage	VDD	–0.3	22	V
	SW	–5	27
	BOOT	–0.3	30
	BOOT-SW, HDRV-SW (Differential from BOOT or HDRV to SW)	–0.3	7
	VSNS+, TRACK, SYNC, FB	–0.3	7
	DATA, CLK, CNTL	–0.3	3.6
	ISNS+, ISNS–	–0.3	15
	VSNS–	–0.3	0.3
Output voltage	HDRV	–0.3	30	V
	BP3	–0.3	3.8
	BP6, COMP, PGOOD, DIFFO, LDRV	–0.3	7
	SMBALRT, ADDR0, ADDR1	–0.3	3.6
Operating junction temperature, T_J		–40	150	°C
Storage Temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_DD	Controller input voltage	3	20	V
T_J	Operating junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS40400	UNIT
		RHL (VQFN)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	31.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise stated, these specifications apply for –40°C ≤ T_J ≤ 125°C, V_DD= 12 Vdc, FREQUENCY_SWITCH = 600 kHz

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY
V_VDD	Input voltage range		3		20	V
I_VDD	Input operating current	Switching, no driver load		6	15	mA
VOLTAGE REFERENCE
V_FB	Feedback pin voltage default settings		594	600	606	mV
V_FB(max)	Feedback pin voltage maximum adjustment			750		mV
V_FB(min)	Feedback pin voltage minimum adjustment			450		mV
V_FB(inc)	Feedback pin voltage adjustment resolution			2.34		mV
V_FB(NL)	Maximum nonlinearity error over adjustment range				10	mV
BP6 REGULATOR
V_BP6	6-V regulator output voltage		6.2	6.5	6.8	V
V_DO6	Regulator dropout voltage, (V_VDD – V_BP6)	V_VDD = 6 V, I_BP6 = 50 mA			300	mV
I_BP6	Regulator current limit		100			mA
BP3 REGULATOR
V_BP3	3.3-V regulator output voltage		3.1	3.3	3.5	V
V_DO3	Regulator dropout voltage, (V_VDD – V_BP3)	V_VDD = 3 V, I_BP3 = 5 mA		100	200	mV
OSCILLATOR
f_SW	Switching frequency	Factory default setting	480	600	720	kHz
	Nominal frequency range		200		2000	kHz
	Accuracy	3 V ≤ V_VDD ≤ 20 V, 200 kHz ≤ f_SW ≤ 2 MHz	–20%		20%
V_IH	SYNC high-level input voltage		2			V
V_IL	SYNC low-level input voltage				0.4	V
I_SYNC	SYNC pin leakage current	V_SYNC = 6 V			100	nA
I_SYNC	SYNC pin leakage current	V_SYNC = 0 V			100	nA
t_SRISE	Maximum SYNC rise time⁽¹⁾		100			ns
t_SYNC	Minimum SYNC pulse width		100			ns
V_RMP	Ramp amplitude⁽¹⁾	FREQUENCY_SWITCH = 200 kHz	V_VDD/6.6	V_VDD/6.5	V_VDD/6.3	V
		FREQUENCY_SWITCH = 600 kHz	V_VDD/7.0	V_VDD/6.8	V_VDD/6.6
		FREQUENCY_SWITCH = 2000 kHz	V_VDD/10	V_VDD/9.6	V_VDD/9.2
V_VLY	Valley voltage⁽¹⁾			0.9
f_SYNC	SYNC range % of nominal oscillator frequency	200 kHz ≤ f_SW ≤ 2 MHz	85%		150%
PULSE WIDTH MODULATOR (PWM)
D_MAX	Maximum duty cycle⁽¹⁾ ⁽⁹⁾	FREQUENCY_SWITCH = 600 kHz	90%
		FREQUENCY_SWITCH = 1.2 MHz	85%
		FREQUENCY_SWITCH = 2 MHz	75%
t_OFF(min)	Minimum OFF time			170	225	ns
t_ON(min)	Minimum controllable pulse⁽¹⁾	T_J = 25°C, f_SW= 600 kHz			75	ns
SOFT-START
t_SS	Soft-start time⁽⁶⁾	Factory default setting	2.7	3.1	3.5	ms
t_SS	Accuracy	600 μs ≤ t_SS ≤ 9 ms	–15%		15%
ERROR AMPLIFIER
GBWP	Gain bandwidth product⁽¹⁾		15	20		MHz
A_OL	DC gain⁽¹⁾		60			dB
I_IBFB	Input bias current: FB (out of pin)		0		100	nA
I_IBT	Input bias current: TRACK (out of pin)		0		250	nA
I_EAOP	Output source current	V_FB = 0 V, V_COMP ≥ 2 V	1			mA
I_EAOM	Output sink current	V_FB = 2 V, V_COMP ≤ 0.3 V	1			mA
V_COMPH	Error amplifier high output voltage	V_FB = 0 V	3.8			V
V_COMPL	Error amplifier low output voltage	V_FB = 2 V			50	mV
V_TRACK(ofst)	TRACK pin offset voltage		–5		5	mV
CURRENT SENSE AMPLIFIER
I_ISNS+	ISNS+ bias current				200	nA
I_ISNS–	ISNS– bias current				100	μA
V_ICM	Input common-mode range		0.45		15	V
AO_CM	Common-mode gain				–80	dB
V_LIN	Input linear range, VISNS+ - VISNS-⁽²⁾		–45		110	mV
CURRENT LIMIT PROTECTION
t_OFF	Off time between restart attempts			6 × t_SS		ms
V_ILIMTH	V_CS+ – V_CS– voltage that trips OC fault function	Factory default settings⁽²⁾, T_J = 25°C	27	30	33	mV
	Threshold accuracy	3 V ≤ V_VDD ≤ 20 V, 30 mV ≤ V_ILIMTH ≤ 110 mV, T_J = 25°C	–10%		10%
	Threshold accuracy	3V ≤ V_VDD ≤ 20 V, V_ILIMTH ≤ 30 mV, T_J = 25°C	–3		3	mV
	Comparator offset	V_ILIMTH = 30 mV, T_J= 25°C	–3		3	mV
	Temperature coefficient⁽¹⁾			4000		ppm/°C
t_DLYOC	Overcurrent delay	3-mV overdrive, T_J = 25°C		155		ns
V_ILIMW	V_CS+ – V_CS– voltage that sets warning status	Factory default settings, T_J = 25°C	12	15	18	mV
	Threshold accuracy	3 V ≤ V_VDD ≤ 20V, 1.9 mV ≤ V_ILIMTH ≤ 120 mV, T_J = 25°C	–10%		10%
	Threshold accuracy	3V ≤ V_VDD ≤ 20 V, V_ILIMTH < 30 mV, T_J = 25°C	–3		3	mV
	Comparator offset	V_ILIMTH = 20 mV, T_J = 25°C	–3		3	mV
	Temperature coefficient⁽¹⁾			4000		ppm/°C
t_DLYOCW	Overcurrent warning delay⁽¹⁾	3-mV overdrive		250		ns
BOOTSTRAP
V_BOOT	Internal diode voltage drop	I_BOOT= 5 mA		0.7	1	V
I_BOOT(lk)	BOOT diode leakage current⁽¹⁾	(V_BOOT – V_SW) = 6 V		1		μA
UVLO
V_UVLO(on)	VDD UVLO turn on threshold⁽⁷⁾	Factory default settings (minimum)	2.475	2.75	3.025	V
V_UVLO(on)	Accuracy⁽⁷⁾	2.25 V ≤ V_VDD ≤ 20 V, 2.75 V ≤ VIN_ON ≤ 18 V	–10%		10%	V
V_UVLO(off)	VDD UVLO turnoff threshold⁽⁷⁾	Factory default settings (minimum)	2.25	2.5	2.75	V
V_UVLO(off)	Accuracy⁽⁷⁾	2.25 V < V_VDD < 20 V, 2.75 V < VIN_OFF < 17.6 V	–10%		10%	V
REMOTE VOLTAGE SENSE AMPLIFIER
V_IOFST	Input offset voltage		–10		10	mV
R_GAIN	Gain-setting resistor⁽¹⁾		48	60	72	kΩ
V_DIFFO	Output voltage at DIFFO pin	V_VDD > 6.5 V	0		6	V
		V_VDD = 5 V	0		4.5
		V_VDD = 3 V	0		2.5
K_DIFF	Differential gain of amplifier		0.995	1	1.005	V/V
V_AGBWP	Closed-loop bandwidth⁽¹⁾		2			MHz
I_VAOP	Output source current	V_SNS+ = V_DIFFO = 5 V, V_SNS– = 0 V	1			mA
I_VAOM	Output sink current	V_SNS+ = 0 V, V_SNS– = 4.5 V, V_DIFFO = 5 V	1			mA
POWERGOOD
V_PGON	FB pin voltage upper limit for power good on	Factory default settings		648		mV
	FB pin voltage lower limit for power good on	Factory default settings		552		mV
	Accuracy	540 mV < V_PGON < 660 mV	–5%		5%
V_PGOFF	FB pin voltage upper limit for power good off	Factory default settings		660		mV
	FB pin voltage lower limit for power good off	Factory default settings		540
	Accuracy	528 mV < V_PGOFF < 672 mV	–5%		5%
R_PGD	Pulldown resistance of PGD pin	V_FB = 0, I_PGOOD = 5 mA			50	Ω
I_PGDLK	Leakage current	Factory default settings , 550 mV < V_FB < 650 mV, V_PGOOD = 5 V	3		15	μA
t_PGD	Delay filter from FB⁽¹⁾			5		μs
OUTPUT VOLTAGE MARGINING
MRG_SLP	VFB slope during margin voltage transition⁽¹⁾	Factory default settings	250	214	188	V/s
MRG_SLP	Accuracy	3 V < V_VDD < 20 V, 600 μs < t_SS < 9 ms	–15%		15%
V_FBMH	FB pin voltage after margin high command	Factory default settings	650	660	670	mV
V_FBML	FB pin voltage after margin low command	Factory default settings	532	540	548	mV
V_FBM(max)	Maximum FB pin voltage with margin		742	750	758	mV
V_FBM(min)	Minimum FB pin voltage with margin		445	450	455	mV
V_FB(inc)	Resolution of FB steps with margin			2.34		mV
OVERVOLTAGE AND UNDERVOLTAGE DETECTION
V_OV	FB pin overvoltage threshold (OV flag)	Factory default settings	638	672	705	mV
V_OV	Accuracy	3 V < V_VDD < 20 V, 648 mV < V_OV < 690 mV	–5%		5%	mV
V_UV	FB pin undervoltage threshold (UV flag)	Factory default settings	502	528	554	mV
V_UV	Accuracy	3 V < V_VDD < 20 V, 510 mV < V_OV < 552 mV	–5%		5%	mV
PMBus INTERFACE
V_IH	High-level input voltage, CLK, DATA, CNTL		2.1			V
V_IL	Low-level input voltage, CLK, DATA, CNTL				0.8	V
I_IH	High-level input current, CLK, DATA, CNTL		–10		10	μA
I_IH	CNTL		–12		10	μA
I_IL	Low-level input current, CLK, DATA, CNTL		–10		10	μA
I_IL	CNTL		–12		10	μA
V_OL	Low-level output voltage, DATA, SMBALRT	3 V ≤ V_VDD ≤ 20 V, I_OUT = 2 mA			0.4	V
I_OH	High-level open-drain leakage current, DATA, SMBALRT	V_OUT = 3.6 V	0		10	μA
C_O ⁽¹⁾	Pin capacitance, CLK, DATA			0.7		pF
f_PMB	PMBus operating frequency range	Slave mode	10		400	kHz
PMBus ADDRESSING
I_ADD	ADDX pin current		8.23	9.75	11.21	μA
V_ADD(L)	Address pin illegal low voltage threshold				0.055	V
MEASUREMENT SYSTEM
t_IDLY	Read delay time⁽³⁾		153	192	231	μs
I_RES	Current measurement resolution (LSB)⁽¹⁰⁾⁽⁵⁾			122		μV
I_RNG	Current measurement range⁽⁵⁾ ⁽⁴⁾		–45		110	mV
I_ACC	Gain accuracy⁽⁸⁾		–3%		3%
I_OFST	Offset		–3		3	mV
V_OUT(res)	VOUT measurement resolution (LSB)			15.625		mV
V_OUT(rng)	VOUT voltage measurement range		0		14	V
V_OUT(gain)	Gain accuracy⁽⁸⁾⁽¹⁾		–2		2	LSB
V_{OUT(gain_adj)}	Gain adjustment range through PMBus		–10%		10%
V_OUT(ofst)	Offset⁽⁸⁾⁽¹⁾		–3%		3%
V_{OUT(ofst_adj)}	Gain adjustment range through PMBus		–125		124	mV
V_IN(res)	V_INmeasurement resolution			32.5		mV
V_IN(rng)	V_IN voltage measurement range		3		20	V
V_IN(gain)	Gain accuracy⁽⁸⁾⁽¹⁾		–2%		2%
V_{IN(gain_adj)}	Gain adjustment range through PMBus		–10%		10%
V_IN(offst)	Offset⁽⁸⁾⁽¹⁾		–5.5	–2	1.4	LSB
V_{IN(offst_adj)}	Offset adjustment range through PMBus		–2		1.968	V
THERMAL SHUTDOWN
T_JSD	Junction OT shutdown temperature⁽¹⁾		135	145	155	°C
T_JSDH	Shutdown hysteresis⁽¹⁾		25	30	35	°C
T_JWRN	Junction OT warning threshold⁽¹⁾		120	130	140	°C
T_JWRNH	Junction OT warning temperature hysteresis⁽¹⁾		15	20	25	°C

(1) Specified by design. Not production tested.

(2) The entire current ripple waveform must remain within the linear range for current reading results to be accurate. DC current level must be zero or greater for accurate results. Current sense does not support applications that sink current. Transient voltages (such as ripple) are permitted to fall below 0 V, but must be within the specified linear range.

(3) All read backs are an average of 16 consecutive measurements – not a rolling average. Time is a delay between parameter updates.

(4) Current reading is only supported to 0 average. Voltage transients to –45 mV are taken into account when computing this average.

(5) Voltage is converted to current by dividing by IOUT_CAL_GAIN, the effective value of the resistance used to sense current in the application. Maximum amount that can be reported through PMBus is 64 A.

(6) See Application and Implementation section for more information regarding soft-start time setting.

(7) Although specifications appear to overlap, hysteresis is assured for UVLO turnon and turnoff thresholds.

(8) PMBus commands provide for calibration of each device on an individual basis for improved overall system accuracy.

(9) Operation at 3 V reduces maximum duty cycle by approximately 5%.

(10) Constrained by the resolution of READ_IOUT command. This presents as the greater of 122 µV/ IOUT_CAL_GAIN or 62.5 mA, the resolution of the READ_IOUT command

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
R_HDHI	High-side driver pullup resistance	(V_BOOT – V_SW) = 6.4 V, I_HDRV = –100 mA, T_J = 25°C		1.25	2.5	Ω
R_HDLO	High-side driver pulldown resistance	(V_BOOT – V_SW) = 6.4 V, I_HDRV = 100 mA, T_J = 25°C		1.3	2.6	Ω
R_LDHI	Low-side driver pullup resistance	T_J = 25°C		1.25	2.5	Ω
R_LDLO	Low-side driver pulldown resistance	T_J = 25°C		0.8	1.5	Ω
t_HRISE	High-side driver rise time⁽¹⁾	C_LOAD = 2.2 nF		6	12.1	ns
t_HFALL	High-side driver fall time⁽¹⁾	C_LOAD = 2.2 nF	6.3	12.6		ns
t_LRISE	Low-side driver rise time⁽¹⁾	C_LOAD = 2.2 nF	6	12.1		ns
t_LFALL	Low-side driver fall time⁽¹⁾	C_LOAD = 2.2 nF	4	8		ns
t_DT	Anti-cross conduction time	MFR_SPECIFIC_00 bit 0 = 0, (short dead time.)	20		50	ns
I_SW	SW pin leakage current (out of pin)	V_SW = 0 V			1	µA