JAJS455B December   2009  – July 2017 TPS43331-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  I2C Interface Electrical Characteristics
    7. 6.7  Switching Regulators Electrical Characteristics
    8. 6.8  Standby Regulator (VSTBY) Electrical Characteristics
    9. 6.9  Linear Regulator (VLR) Electrical Characteristics
    10. 6.10 High-Side Driver (HSD) Electrical Characteristics
    11. 6.11 AC Switching Characteristics
    12. 6.12 I2C Interface Switching Characteristics
    13. 6.13 Switching Regulators Switching Characteristics
    14. 6.14 Linear Regulator Switching Characteristics
    15. 6.15 High-Side Driver (HSD) Switching Characteristics
    16. 6.16 Timing and Switching Diagrams
    17. 6.17 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Unregulated Battery Input Voltage (VBAT)
      2. 7.3.2  Protected Unregulated Battery Input Voltage (VBATP)
      3. 7.3.3  Low-Voltage Warning Input (LVWIN)
      4. 7.3.4  Voltage Warning Output (VBATW)
      5. 7.3.5  Low-Voltage Reset (RST)
      6. 7.3.6  Power-Good Delay Timer Input (PGDLY)
      7. 7.3.7  Active Mode Enable Input (EN)
      8. 7.3.8  Slew Rate Control Capacitor Input (CSLEW)
      9. 7.3.9  Charge Pump Capacitor Input (VCP)
      10. 7.3.10 Power Ground (PGND)
      11. 7.3.11 Analog Ground Reference (AGND)
      12. 7.3.12 Inter-IC Communications Interface (I2CID)
      13. 7.3.13 Clock Input (SCL)
      14. 7.3.14 Data Line (SDA)
      15. 7.3.15 Interface Chip Identifier (I2CID)
      16. 7.3.16 Switch Mode Regulators
      17. 7.3.17 Upper FET Gate Drive Outputs (VGT1 and VGT2)
      18. 7.3.18 Lower FET Gate Driver Outputs (VGB1 and VGB2)
      19. 7.3.19 Bootstrap Capacitor Input (CBS1 and CBS2)
      20. 7.3.20 Phase Reference for High-Side Bootstrap Supply (PH1 and PH2)
      21. 7.3.21 Current Sense High-Side (ISHI1 and ISHI2)
      22. 7.3.22 Current Sense Low-Side (ISLO1 and ISLO2)
      23. 7.3.23 Regulated Output Sense Voltage Feedback (VFB1 and VFB2)
      24. 7.3.24 Feedback Compensation Input (VCMP1 and VCMP2)
      25. 7.3.25 Synchronization Input (SYNCH)
      26. 7.3.26 Standby Linear Regulator Input (VINSB)
      27. 7.3.27 Standby Regulator Output (VSTBY)
      28. 7.3.28 Standby Regulator Sense Voltage (VSTBYS)
      29. 7.3.29 Switched Linear Regulator Input (VINLR)
      30. 7.3.30 Switched Linear Regulator Output (VLR)
      31. 7.3.31 Switched Linear Regulator Sense Voltage (VLRS)
      32. 7.3.32 High-Side Driver Output (HSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Mode Definition
    5. 7.5 Programming
      1. 7.5.1 Register Definition for I2C
        1. 7.5.1.1 Chip Address Byte
    6. 7.6 Register Map
      1. 7.6.1 Data Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Type II Compensation
        2. 8.2.2.2 Type III Compensation
        3. 8.2.2.3 Component Calculations
          1. 8.2.2.3.1 Buck-Controllers (VBUCK1, VBUCK2)
        4. 8.2.2.4 Power Dissipation
        5. 8.2.2.5 Buck Regulators
          1. 8.2.2.5.1 Buck Regulator 1 (VBUCK 1)
            1. 8.2.2.5.1.1 Step 1. Calculate the Inductor Value
            2. 8.2.2.5.1.2 Step 2. Inductor Peak Current
            3. 8.2.2.5.1.3 Step 3. Calculating the Output Capacitance (CO)
            4. 8.2.2.5.1.4 Step 4. Calculating Loop Compensation Values
          2. 8.2.2.5.2 Buck Regulator 2 (VBUCK 2)
            1. 8.2.2.5.2.1 Step 5. Calculate the Inductor Value
            2. 8.2.2.5.2.2 Step 6. Inductor Peak Current
            3. 8.2.2.5.2.3 Step 7. Calculating the Output Capacitance (CO)
            4. 8.2.2.5.2.4 Step 8. Calculating Loop Compensation Values
      3. 8.2.3 Application Curves
    3. 8.3 System Example
      1. 8.3.1 Multiple Power Supply Configuration for Vehicle Audio Applications
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding and Circuit Layout Considerations
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Derating
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 改訂履歴

Changes from A Revision (September 2015) to B Revision

  • Added 「特長」セクションに車載の特長をGo
  • Changed the values for the linear regulator and standby regulator in the Recommended Operating Conditions tableGo
  • Added the VBAT = 6 V test condition and change VUVLO to 9 V in the battery < 18 V test condition for the battery input leakage current parameter in the DC Electrical Characteristics tableGo
  • Added back the 18-V test condition (8% maximum) for the VSTBY parameterGo
  • Added to the Charge Pump Capacitor Input (VCP) sectionGo
  • Updated some of the symbols in the Detailed Design Procedure sectionGo
  • Added 「ドキュメントの更新通知を受け取る方法」セクションGo
  • Changed 「静電放電に関する注意事項」の記載Go

Changes from * Revision (December 2009) to A Revision

  • Added 「ESD定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションGo
  • Added Thermal Information table Go
  • Deleted parameter VSTBY = 18 for 8 MAX.Go
  • Changed Input voltage in Table 3 Go
  • Changed VBUCK 1 to IBUCK 1 in Table 3 Go
  • Changed VBUCK 2 to IBUCK 2 in Table 3 Go