9.2.3 Parallel Operation

Configuring two TPS50601-SP in order to provide 12-A output current.

Design procedure is as follows - An example, Figure 30, shows parallel configuration using two TPS50601-SP in Master/Slave.

Important design steps are detailed as follows:

Figure 30. Parallel Configuration Showing Master and Slave

For the master - RT pin must be left floating and this will set the frequency to 500 kHz.

In order to parallel two current mode control POLs (TPS50601-SP) one needs to do the following:

1. RT pin on master must be left open (switching frequency 500-kHz typical (395-kHz minimum to 585-kHz maximum)) as highlighted in the data sheet frequency internally generated. For more details, see Adjustable Switching Frequency and Synchronization (SYNC) section.
   1. When RT pin is left open then sync pin becomes output.
2. RT pin on slave should be selected within 5% of master ie RT = 96-kHz typical.
3. Have a single feedback loop.
4. Sync pins of master must be connected to sync pins of slave.
5. Connect comp pins of two POLs together.
6. Connect Vsense pins of two POLs together.
7. Connect SS pins together.
8. Connect enable pins together thus there is one enable.

Figure 31. Parallel Configuration With External Sync

Configuration when using an external clock is as follows: Refer to Figure 31.

1. Master/slave configuration can also be achieved if desired using external clock ie if operating at 100 kHZ or any other customer selected frequency.
   1. External user supplied clock signal is required.
   2. RT pins of both master and slave must be populated with appropriate resistor value ie 475 kΩ (for 100 kHZ).
   3. Slave signal feeding the sync pin must be inverter.
2. RT pin on both master and slave must be populated for 100 kHz operation RT = 495 kΩ.
3. External user supplied clock signal is required.
4. Connect comp pins of two POLs together.
5. Connect Vsense pins of two POLs together.
6. Connect SS pins together.
7. Connect enable pins together thus there is one enable.