SLUSBA6B December 2012 – October 2015 TPS51604
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS51604 driver is optimized for high-frequency CPU VCORE applications. Advanced features such reduced dead-time drive and Auto Zero Crossing are used to optimize efficiency over the entire load range.
The design example uses the input parameters summarized in Table 2.
|VP_P||Output ripple voltage||IOUT = 12 A||20||mV|
|η||Efficiency||IOUT = 12 A, VIN - 12 V||80%|
A 5-V power supply is suggested for VDD. Placed a ceramic capacitor with a value of 1 uF or greater between VDD and GND.
The boot capacitor is the power supply for high-side driver. Place a ceramic capacitor with a value of 0.1 µF or greater between the BST pin and the SW pin.
To reduce the voltage spike on switch node, use a boot resistor with a value of several Ohms in series with boot capacitor to slow the turn-on of high-side FET.
Connect the PWM pin of the TPS51604 device to the PWM pin of the controller. The TRIP pins can be used for DCM mode or very-low-power state. Leave the TRIP pin floating if it is not in use.
Connect the DRVH pin of the TPS51604 device to the gate of the high-side FET of the power block. Connect the DRVL pin of the TPS51604 device to the gate of the low-side FET of the power block. Connect the SW pins of the TPS51604 device to the switch node as required by the high-side driver fo the power block.
|VIN = 12 V||IOUT = 0 A|
|fSW = 1 MHz|
|VIN = 7.2 V||IOUT = 12 A|