SLUSBA6B December   2012  – October 2015 TPS51604

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
    7. 6.7 Typical Power Block MOSFET Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO Protection
      2. 7.3.2 PWM Pin
      3. 7.3.3 SKIP Pin
        1. 7.3.3.1 Zero Crossing (ZX) Operation
      4. 7.3.4 Adaptive Dead-Time Control and Shoot-Through Protection
      5. 7.3.5 Integrated Boost-Switch
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Step 1: Select the Input (VDD) Capacitor
        2. 8.2.2.2 Step 2: Select Boot Capacitor and Boot Resistor
        3. 8.2.2.3 Step 3: Establish Connection Between TPS51604 and Controller
        4. 8.2.2.4 Step 4: Establish Connection Between TPS51604 and the Power Block
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1) (2)

over operating free-air temperature (unless otherwise noted)
MIN MAX UNIT
Input voltage VDD –0.3 6 V
PWM, SKIP –0.3 6
Output voltage BST –0.3 35 V
BST (transient <20 ns) –0.3 38
BST to SW; DRVH to SW –0.3 6
SW –2 30
DRVH, SW (transient <20 ns) –5 38
DRVL –0.3 6
Ground pins GND to PAD –0.3 0.3 V
Operating junction temperature, TJ –40 125 °C
Storage temperature range, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 ±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage VDD 4.5 5 5.5 V
PWM, SKIP –0.1 5.5
Output voltage BST –0.1 34 V
BST to SW; DRVH to SW –0.1 5.5
SW –1 28
DRVL –0.1 5.5
Ground pins GND to PAD –0.1 0.1 V
Operating junction temperature, TJ –40 105 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS51604 UNIT
WSON (DSG)
8 PINS
RθJA Junction-to-ambient thermal resistance 63.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 74.1 °C/W
RθJB Junction-to-board thermal resistance 34.3 °C/W
ψJT Junction-to-top characterization parameter 2.0 °C/W
ψJB Junction-to-board characterization parameter 34.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 11.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

These specifications apply for –40°C ≤ TJ ≤ 105°C, and VVDD = 5 V unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD INPUT SUPPLY
ICC Supply current (operating) VSKIP = VVDD or VSKIP = 0 V,
PWM = High		 160 600 µA
VSKIP = VVDD or VSKIP = 0 V,
PWM = Low		 250
VSKIP = VVDD or VSKIP = 0 V,
PWM = Float		 130
VSKIP = Float 8
VDD UNDERVOLTAGE LOCKOUT (UVLO)
VUVLO UVLO threshold Rising threshold 4.15 V
Falling threshold 3.7
VUVHYS UVLO hysteresis 0.2 V
PWM AND SKIP I/O SPECIFICATIONS
RI Input impedance Pullup to VDD 1.7 MΩ
Pulldown (to GND) 800 kΩ
VIL Low-level input voltage 0.6 V
VIH High-level input voltage 2.65 V
VIHH Hysteresis 0.2 V
VTS Tri-state voltage 1.3 2.0 V
tTHOLD(off1) Tri-state activation time (falling) PWM 60 ns
tTHOLD(off2) Tri-state activation time (rising) PWM 60 ns
tTSKF Tri-state activation time (falling) SKIP 1 µs
tTSKR Tri-state activation time (rising) SKIP 1 µs
t3RD(PWM) Tri-state exit time PWM 100 ns
t3RD(SKIP) Tri-state exit time SKIP 50 µs
HIGH-SIDE GATE DRIVER (DRVH)
tR(DRVH) Rise time DRVH rising, CDRVH = 3.3 nF; 20% to 80% 30 ns
tRPD(DRVH) Rise time propogation delay CDRVH = 3.3 nF 40 ns
RSRC Source resistance Source resistance,
(VBST– VSW) = 5 V,
high state, (VBST – VDRVH) = 0.1 V		 4 8 Ω
tF(DRVH) Fall time DRVH falling, CDRVH = 3.3 nF 8 ns
tFPD(DRVH) Fall-time propagation delay CDRVH = 3.3 nF 25 ns
RSNK Sink resistance Sink resistance,
(VBST – VSW) forced to 5 V,
low state (VDRVH – VSW) = 0.1 V		 0.5 1.6 Ω
RDRVH DRVH to SW resistance(1) 100 kΩ
LOW-SIDE GATE DRIVER (DRVL)
tR(DRVL) Rise time DRVL rising, CDRVL = 3.3 nF; 20% to 80% 15 ns
tRPD(DRVL) Rise time propagation delay CDRVL = 3.3 nF 35 ns
RSRC Source resistance Source resistance, (VVDD–GND) = 5 V,
high state, (VVDD – VDRVL) = 0.1 V		 1.5 3 Ω
tF(DRVL) Fall time DRVL falling, CDRVL = 3.3 nF 10 ns
tFPD(DRVL) Fall-time propagation delay CDRVL= 3.3 nF 15 ns
RSNK Sink resistance Sink resistance, (VVDD– GND) = 5 V,
low state, (VDRVL – GND) = 0.1 V		 0.4 1.6 Ω
RDRVL DRVL to GND resistance(1) 100 kΩ
GATE DRIVER DEAD-TIME
tR(DT) Rising edge 0 20 35 ns
tF(DT) Falling edge 0 10 25 ns
ZERO CROSSING COMPARATOR
VZX Zero crossing offset SW voltage rising –2.25 0 2.00 mV
BOOTSTRAP SWITCH
VFBST Forward voltage IF = 10 mA 120 240 mV
IRLEAK Reverse leakage (VBST – VVDD) = 25 V 2 µA
RDS(on) On-resistance 12 24 Ω
(1) Specified by design. Not production tested.

6.6 Typical Characteristics

TPS51604 wave01_lusba6.png
Figure 1. PWM High to DRVL Low
TPS51604 wave03_lusba6.png
Figure 3. DRVL Low to DRVH High
TPS51604 wave05_lusba6.png
Figure 5. PWM Low to Tri-State
TPS51604 wave07_lusba6.png
Figure 7. SKIP Mode Entry
TPS51604 wave09_lusba6.png
Figure 9. Very-Low-Power Mode Entry
TPS51604 wave11_lusba6.png
VIN = 8 V
Figure 11. SW Node-Ringing
TPS51604 wave02_lusba6.png
Figure 2. PWM Low to DRVH Low
TPS51604 wave04_lusba6.png
Figure 4. DRVH Low to DRVL High
TPS51604 wave06_lusba6.png
Figure 6. PWM Tri-State to Low
TPS51604 wave08_lusba6.png
Figure 8. SKIP Mode Exit
TPS51604 wave10_lusba6.png
Figure 10. Very-Low-Power Mode Exit
TPS51604 wave12_lusba6.png
VIN = 20 V
Figure 12. SW Node-Ringing

6.7 Typical Power Block MOSFET Characteristics

Power block MOSFET: CSD87330, Inductor: 0.22 µF, 1.1-mΩ DCR
TPS51604 D004_SLUSBA6.gif
FCCM VOUT = 1.8 V
VIN = 7.4 V fSW = 800 kHz
Figure 13. Efficiency vs Output Current, FCCM
TPS51604 D003_SLUSBA6.gif
Skip Mode VOUT = 1.8 V
VIN = 7.4 V fSW = 800 kHz
Figure 14. Efficiency vs Output Current, SKIP Mode